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Joakim Urdahl
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2020 – today
- 2020
- [j3]Tobias Ludwig
, Joakim Urdahl, Dominik Stoffel
Properties First - Correct-By-Construction RTL Design in System-Level Design Flows. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3093-3106 (2020)
2010 – 2019
- 2019
- [j2]Shrinidhi Udupi
Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1262-1275 (2019) - 2018
- [c10]Mohammad Rahmani Fadiheh, Joakim Urdahl, Srinivasa Shashank Nuthakki
Symbolic quick error detection using symbolic initial state for pre-silicon verification. DATE 2018: 55-60 - 2017
- [c9]Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Dynamic Power Optimization based on Formal Property Checking of Operations. MBMV 2017: 129-136 - [c8]Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Dynamic Power Optimization Based on Formal Property Checking of Operations. VLSID 2017: 227-232 - 2016
- [b1]Joakim Urdahl:
Path Predicate Abstraction: for Sound System-Level Modeling of Digital Circuits. Kaiserslautern University of Technology, Germany, Shaker 2016 - [c7]Joakim Urdahl, Shrinidhi Udupi, Tobias Ludwig, Dominik Stoffel, Wolfgang Kunz:
Properties first? a new design methodology for hardware, and its perspectives in safety analysis. ICCAD 2016: 84 - 2015
- [c6]Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Architectural system modeling for correct-by-construction RTL design. FDL 2015: 90-97 - [c5]Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Architectural System Modeling for Correct-by-Construction RTL Design. MBMV 2015: 93-104 - 2014
- [j1]Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Path Predicate Abstraction for Sound System-Level Models of RT-Level Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 291-304 (2014) - [c4]Wolfgang Kunz, Dominik Stoffel, Joakim Urdahl:
T4B: Formal verification in system-on-chip design: Scientific foundations and practical methodology. SoCC 2014: xlv-xlvi - 2013
- [c3]Joakim Urdahl, Shrinidhi Udupi, Dominik Stoffel, Wolfgang Kunz:
Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design. PATMOS 2013: 67-74 - 2012
- [c2]Joakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz:
System verification of concurrent RTL modules by compositional path predicate abstraction. DAC 2012: 334-343 - 2010
- [c1]Joakim Urdahl, Dominik Stoffel, Jörg Bormann, Markus Wedler, Wolfgang Kunz:
Path predicate abstraction by complete interval property checking. FMCAD 2010: 207-215
Coauthor Index
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