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Ravishankar Arunachalam
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2000 – 2009
- 2005
- [c8]Aniket, Ravishankar Arunachalam:
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits. VLSI Design 2005: 479-484 - 2004
- [c7]Siddharth Garg, Siddharth Tata, Ravishankar Arunachalam:
Static Transition Probability Analysis Under Uncertainty. ICCD 2004: 380-386 - 2003
- [c6]Emrah Acar, Ravishankar Arunachalam, Sani R. Nassif:
Predicting short circuit power from timing models. ASP-DAC 2003: 277-282 - [c5]Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif:
Optimal shielding/spacing metrics for low power design. ISVLSI 2003: 167-172 - 2002
- [j1]Ravishankar Arunachalam, Ronald DeShawn Blanton, Lawrence T. Pileggi
:
Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation. VLSI Design 15(3): 605-618 (2002) - 2001
- [c4]Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi
False Coupling Interactions in Static Timing Analysis. DAC 2001: 726-731 - 2000
- [c3]Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
TACO: timing analysis with coupling. DAC 2000: 266-269
1990 – 1999
- 1998
- [c2]Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
Determination of worst-case aggressor alignment for delay calculation. ICCAD 1998: 212-219 - 1997
- [c1]Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi
CMOS Gate Delay Models for General RLC Loading. ICCD 1997: 224-229
Coauthor Index
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