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Chandra Tirumurti
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2010 – 2019
- 2017
- [j9]Martin Omaña
, Daniele Rossi
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 238-246 (2017) - 2016
- [j8]Martin Omaña, Daniele Rossi
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. IEEE Trans. Computers 65(8): 2484-2494 (2016) - 2015
- [j7]Michail Maniatakos
Revisiting Vulnerability Analysis in Modern Microprocessors. IEEE Trans. Computers 64(9): 2664-2674 (2015) - 2014
- [c11]Martin Omaña, Daniele Rossi
Power droop reduction during Launch-On-Shift scan-based logic BIST. DFT 2014: 21-26 - 2013
- [j6]Naghmeh Karimi, Michail Maniatakos
On the Impact of Performance Faults in Modern Microprocessors. J. Electron. Test. 29(3): 351-366 (2013) - [c10]Martin Omaña, Daniele Rossi
Novel approach to reduce power droop during scan-based logic BIST. ETS 2013: 1-6 - 2012
- [j5]Michail Maniatakos
Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors. IEEE Trans. Computers 61(10): 1361-1370 (2012) - [j4]Hongxia Fang, Krishnendu Chakrabarty
Functional Test-Sequence Grading at Register-Transfer Level. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1890-1894 (2012) - 2011
- [j3]Michail Maniatakos
Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller. IEEE Trans. Computers 60(9): 1260-1273 (2011) - [j2]Naghmeh Karimi, Michail Maniatakos
Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor. IEEE Trans. Computers 60(9): 1274-1287 (2011) - [c9]Michail Maniatakos
AVF Analysis Acceleration via Hierarchical Fault Pruning. ETS 2011: 87-92 - 2010
- [c8]Daniele Rossi
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. Conf. Computing Frontiers 2010: 113-114
2000 – 2009
- 2009
- [c7]Naghmeh Karimi, Michail Maniatakos
Impact analysis of performance faults in modern microprocessors. ICCD 2009: 91-96 - [c6]Michail Maniatakos
Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller. VTS 2009: 9-14 - [c5]Hongxia Fang, Krishnendu Chakrabarty
RT-Level Deviation-Based Grading of Functional Test Sequences. VTS 2009: 264-269 - 2008
- [c4]Michail Maniatakos
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller. DFT 2008: 454-462 - 2007
- [c3]Hossein Asadi
Estimating Error Propagation Probabilities with Bounded Variances. DFT 2007: 41-49 - 2005
- [j1]Sandip Kundu, Sujit T. Zachariah, Yi-Shing Chang, Chandra Tirumurti:
On modeling crosstalk faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1909-1915 (2005) - 2004
- [c2]Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang:
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. DATE 2004: 1078-1083 - 2003
- [c1]Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti:
On Modeling Cross-Talk Faults. DATE 2003: 10490-10495
Coauthor Index
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