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Adam Milik
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2010 – 2019
- 2018
- [j4]Adam Milik
:
Multiple-Core PLC CPU Implementation and Programming. J. Circuits Syst. Comput. 27(10): 1850162:1-1850162:30 (2018) - 2017
- [j3]Adam Milik
Nonlinearity Measurement of a Voltage Ramp Using a Digital Technique. J. Circuits Syst. Comput. 26(5): 1750081:1-1750081:15 (2017) - 2016
- [j2]Adam Milik
On hardware synthesis and implementation of PLC programs in FPGAs. Microprocess. Microsystems 44: 2-16 (2016) - 2013
- [c11]Adam Milik
On Hardware Synthesis of Reconfigurable Logic Controllers from Ladder Diagrams According to IEC61131-3. PDeS 2013: 256-261 - 2012
- [c10]Adam Milik:
On mapping of DSP48 units for arithmetic operation in reconfigurable logic controllers. PDeS 2012: 249-254 - [c9]Andrzej Pulka
Dynamic rescheduling of tasks in time predictable embedded systems. PDeS 2012: 305-310 - 2011
- [c8]Adam Milik
Automatic implementation of arithmetic operation in reconfigurable logic controllers. ECCTD 2011: 721-724 - 2010
- [j1]Dariusz Kania
Logic synthesis based on decomposition for CPLDs. Microprocess. Microsystems 34(1): 25-38 (2010) - [c7]Adam Milik, Andrzej Pulka
On efficient implementation of search algorithm for genome patterns. PDeS 2010: 22-27 - [e1]Adam Milik, Edward Hrynkiewicz:
10th IFAC Workshop on Programmable Devices and Embedded Systems, PDeS 2010, Gliwice, Poland, October 6-7, 2010. International Federation of Automatic Control 2010, ISBN 978-3-902661-95-1 [contents]
2000 – 2009
- 2009
- [c6]Andrzej Pulka
Multithread RISC architecture based on programmable interleaved pipelining. ICECS 2009: 647-650 - [c5]Adam Milik, Andrzej Pulka
The reconfigurable hardware accelerator for searching genome patterns. PDeS 2009: 33-38 - 2008
- [c4]Andrzej Pulka
VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams. FDL 2008: 118-123 - 2007
- [c3]Adam Milik, Andrzej Pulka:
Common HDL-Matlab Simulation Environment. FDL 2007: 68-73 - 2005
- [c2]Dariusz Kania
A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. DSD 2005: 114-121 - [c1]Dariusz Kania
Decomposition of Multi-Output Functions for CPLDs. DSD 2005: 442-449
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