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Kyu-Myung Choi
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2020 – today
- 2024
- [c21]Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim:
Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. DATE 2024: 1-6 - [c20]Chanhee Jeon, Doyeon Won, Jaewan Yang, Kyu-Myung Choi, Taewhan Kim:
BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost. DATE 2024: 1-6 - 2023
- [c19]Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim:
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. DATE 2023: 1-6 - 2020
- [j5]Taehwan Kim, Kwangok Jeong, Jungyun Choi, Taewhan Kim, Kyu-Myung Choi:
SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage. Integr. 74: 81-92 (2020) - [c18]Jeongwoo Heo, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi:
Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes. ASP-DAC 2020: 139-144
2010 – 2019
- 2019
- [j4]Kyeongrok Jo
, Seyong Ahn, Jungho Do, Taejoong Song
Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1933-1946 (2019) - [c17]Taehwan Kim, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi:
SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage. ISVLSI 2019: 146-151 - 2018
- [c16]Kyeongrok Jo, Seyong Ahn, Taewhan Kim, Kyu-Myung Choi:
Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion. ASP-DAC 2018: 500-506 - 2015
- [j3]Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang
A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications. IEEE J. Solid State Circuits 50(1): 158-169 (2015) - 2014
- [c15]Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang
13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications. ISSCC 2014: 232-233 - 2010
- [j2]Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai:
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. ACM Trans. Design Autom. Electr. Syst. 15(4): 28:1-28:37 (2010) - [j1]Hyung-Ock Kim, Bong Hyun Lee, Jong-Tae Kim, Jung Yun Choi, Kyu-Myung Choi, Youngsoo Shin:
Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 505-509 (2010) - [c14]Kyu-Myung Choi:
An industrial perspective of 3D IC integration technology: from the viewpoint of design technology. ASP-DAC 2010: 544-545
2000 – 2009
- 2009
- [c13]Suk-Soo Pyo, Cheol-Ha Lee, Gyun-Hong Kim, Kyu-Myung Choi, Young-Hyun Jun, Bai-Sun Kong:
45nm Low-power Embedded Pseudo-SRAM with ECC-based Auto-adjusted Self-refresh Scheme. ISCAS 2009: 2517-2520 - 2008
- [c12]Soo-Kwan Eo, Sungjoo Yoo, Kyu-Myung Choi:
An industrial perspective of power-aware reliable SoC design. ASP-DAC 2008: 555-557 - [c11]Woo-Cheol Kwon, Sungjoo Yoo, Sung-Min Hong, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo:
A practical approach of memory access parallelization to exploit multiple off-chip DDR memories. DAC 2008: 447-452 - [c10]Sungpack Hong, Sungjoo Yoo, Byeong Bin, Kyu-Myung Choi, Soo-Kwan Eo, Taehwan Kim:
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution. DATE 2008: 242-247 - [c9]Woo-Cheol Kwon, Sung-Min Hong, Sungjoo Yoo, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo:
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication. DATE 2008: 1244-1249 - 2007
- [i1]Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture. CoRR abs/0710.4808 (2007) - 2006
- [c8]Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
PowerViP: Soc power estimation framework at transaction level. ASP-DAC 2006: 551-558 - [c7]Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi:
Worst case execution time analysis for synthesized hardware. ASP-DAC 2006: 905-910 - [c6]Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study. CODES+ISSS 2006: 235-240 - [c5]Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim:
A systematic IP and bus subsystem modeling for platform-based system design. DATE 2006: 560-564 - [c4]Sungpack Hong, Sungjoo Yoo, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
Runtime distribution-aware dynamic voltage scaling. ICCAD 2006: 587-594 - 2005
- [c3]Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture. DATE 2005: 138-139 - 2004
- [c2]Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design. DATE 2004: 352-357 - 2003
- [c1]Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong:
An MTCMOS design methodology and its application to mobile computing. ISLPED 2003: 110-115
Coauthor Index
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