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Lasse Natvig
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- affiliation: Norwegian University of Science and Technology, Norway
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2020 – today
- 2025
- [j13]Steffen J. S. Bakker
, Mohamed Ben Ahmed
FOMOsim: An open-source simulator for rigorous analysis of micromobility planning problems. Expert Syst. Appl. 264: 125842 (2025) - 2020
- [j12]Juan M. Cebrian
Scalability analysis of AVX-512 extensions. J. Supercomput. 76(3): 2082-2097 (2020)
2010 – 2019
- 2018
- [j11]Abdullah Al Hasib, Juan M. Cebrian
A vectorized k-means algorithm for compressed datasets: design and experimental analysis. J. Supercomput. 74(6): 2705-2728 (2018) - [c36]Benjamin A. Bjørnseth, Jan Christian Meyer, Lasse Natvig:
Make software harder. CF 2018: 236-239 - [i3]Benjamin Andreassen Bjørnseth, Jan Christian Meyer, Lasse Natvig:
Proof-of-Concept Examples of Performance-Transparent Programming Models. CoRR abs/1803.11179 (2018) - 2017
- [c35]Benjamin Andreassen Bjørnseth, Jan Christian Meyer, Lasse Natvig:
Efficient array slicing on the Intel Xeon Phi coprocessor. ARRAY@PLDI 2017: 40-47 - 2016
- [c34]Benjamin A. Bjørnseth, Asbjørn Djupdal, Lasse Natvig:
A systematic approach to automated construction of power emulation models. DATE 2016: 600-605 - [c33]Kameswar Rao Vaddina, Juan M. Cebrian
Transient Temperature Prediction for Aging Thermal Sensors Using Artificial Neural Network. PDP 2016: 51-57 - 2015
- [j10]Juan M. Cebrian
ParVec: vectorizing the PARSEC benchmark suite. Computing 97(11): 1077-1100 (2015) - [j9]Alexandru C. Iordan, Magnus Jahre
Tuning the victim selection policy of Intel TBB. J. Syst. Archit. 61(10): 584-591 (2015) - [c32]Abdullah Al Hasib, Juan M. Cebrian
V-PFORDelta: Data Compression for Energy Efficient Computation of Time Series. HiPC 2015: 416-425 - [c31]Abdullah Al Hasib, Nikita Nikitin, Lasse Natvig:
Cost-comfort balancing in a smart residential building with bidirectional energy trading. SustainIT 2015: 1-6 - [i2]Lasse Natvig, Torbjørn Follan, Simen Støa, Sindre Magnussen, Antonio García-Guirado:
Climbing Mont Blanc - A Training Site for Energy Efficient Programming on Heterogeneous Multicore Processors. CoRR abs/1511.02240 (2015) - 2014
- [j8]Juan M. Cebrian
Performance and energy impact of parallelization and vectorization techniques in modern microprocessors. Computing 96(12): 1179-1193 (2014) - [c30]Alexandru C. Iordan, Magnus Jahre
Victim Selection Policies for Intel TBB: Overheads and Energy Footprint. ARCS 2014: 13-24 - [c29]Abdullah Al Hasib, Nikita Nikitin, Lasse Natvig:
Load scheduling in smart buildings with bidirectional energy trading. IPCCC 2014: 1-2 - [c28]Juan M. Cebrian
Optimized hardware for suboptimal software: The case for SIMD-aware benchmarks. ISPASS 2014: 66-75 - 2013
- [c27]Juan M. Cebrian
Temperature effects on on-chip energy measurements. IGCC 2013: 1-6 - [c26]Alexandru C. Iordan, Magnus Jahre
Challenges of Reducing Cycle-Accurate Simulation Time for TBP Applications. ICCS 2013: 1814-1823 - [c25]Alexandru C. Iordan, Magnus Jahre
On the energy footprint of task based parallel applications. HPCS 2013: 164-171 - [c24]Jan Christian Meyer, Juan M. Cebrian
Energy-Efficient Sparse Matrix Autotuning with CSX - A Trade-off Study. IPDPS Workshops 2013: 931-937 - 2012
- [j7]Mujahed Eleyat, Lasse Natvig:
IPM based sparse LP solver on a heterogeneous processor. Comput. Manag. Sci. 9(2): 287-299 (2012) - [c23]Abdullah Al Hasib, Per Gunnar Kjeldsberg, Lasse Natvig:
Performance and Energy Efficiency Analysis of Data Reuse Transformation Methodology on Multicore Processor. Euro-Par Workshops 2012: 337-346 - [c22]Hallgeir Lien, Lasse Natvig, Abdullah Al Hasib, Jan Christian Meyer:
Case Studies of Multi-core Energy Efficiency in Task Based Programs. ICT-GLOW 2012: 44-54 - [c21]Juan M. Cebrian
Improving Energy Efficiency through Parallelization and Vectorization on Intel Core i5 and i7 Processors. SC Companion 2012: 675-684 - 2011
- [j6]Marius Grannæs, Magnus Jahre, Lasse Natvig:
Storage Efficient Hardware Prefetching using Delta-Correlating Prediction Tables. J. Instr. Level Parallelism 13 (2011) - [j5]Magnus Jahre
A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors. Trans. High Perform. Embed. Archit. Compil. 4: 1-20 (2011) - [c20]Marius Grannæs, Magnus Jahre
Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy. ARCS 2011: 135-146 - [c19]Mujahed Eleyat, Lasse Natvig, Jørn Amundsen:
Cache-Aware Matrix Multiplication on Multicore Systems for IPM-based LP Solvers. FedCSIS 2011: 431-438 - [c18]Mujahed Eleyat, Dag Haugland, Magnus Lie Hetland, Lasse Natvig:
Parallel algorithms for the maximum flow problem with minimum lot sizes. OR 2011: 83-88 - 2010
- [c17]Marius Grannæs, Magnus Jahre
Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. HiPEAC 2010: 247-261 - [c16]Magnus Jahre
DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. HiPEAC 2010: 292-306 - [c15]Mujahed Eleyat, Lasse Natvig:
Mixed-Precision Parallel Linear Programming Solver. SBAC-PAD 2010: 41-46 - [c14]Mujahed Eleyat, Lasse Natvig:
Implementation of a linear programming solver on the Cell BE processor. ICCS 2010: 1055-1064 - [i1]Magnus Jahre, Lasse Natvig:
Computational Computer Architecture Research at NTNU. ERCIM News 2010(81) (2010)
2000 – 2009
- 2009
- [j4]Lasse Natvig, Guttorm Sindre
A compulsory yet motivating question/answer game to teach computer fundamentals. Comput. Appl. Eng. Educ. 17(2): 167-179 (2009) - [j3]Guttorm Sindre
Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals. IEEE Trans. Educ. 52(1): 10-18 (2009) - [c13]Magnus Jahre
A light-weight fairness mechanism for chip multiprocessor memory systems. Conf. Computing Frontiers 2009: 1-10 - [c12]Magnus Jahre
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures. HPCC 2009: 622-629 - 2008
- [c11]Sabri Pllana, Siegfried Benkner, Eduard Mehofer, Lasse Natvig, Fatos Xhafa
Towards an Intelligent Environment for Programming Multi-core Computing Systems. Euro-Par Workshops 2008: 141-151 - [c10]Marius Grannæs, Magnus Jahre
Low-cost open-page prefetch scheduling in chip multiprocessors. ICCD 2008: 390-396 - 2007
- [j2]Haakon Dybdahl, Per Stenström, Lasse Natvig:
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. SIGARCH Comput. Archit. News 35(4): 45-52 (2007) - 2006
- [j1]Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Grannæs, Lasse Natvig:
Destructive-read in embedded DRAM, impact on power consumption. J. Embed. Comput. 2(2): 249-260 (2006) - [c9]Haakon Dybdahl, Marius Grannæs, Lasse Natvig:
Cache Write-Back Schemes for Embedded Destructive-Read DRAM. ARCS 2006: 145-159 - [c8]Cyril Banino-Rokkones, Olivier Beaumont
Master-Slave Tasking on Asymmetric Networks. Euro-Par 2006: 167-176 - [c7]Haakon Dybdahl, Per Stenström, Lasse Natvig:
A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors. HiPC 2006: 22-34 - [c6]Haakon Dybdahl, Per Stenström, Lasse Natvig:
An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. MEDEA@PACT 2006: 45-52 - 2004
- [c5]Lasse Natvig, Steinar Line:
Age of computers: game-based teaching of computer fundamentals. ITiCSE 2004: 107-111 - 2001
- [c4]Lasse Natvig:
Simulating Parallel Architectures with BSPlab. HPCN Europe 2001: 547-550 - [c3]Tormod Njølstad, Lasse Natvig:
Experience from a 450 Students/Year Course on Digital Logic and Computer Fundamentals using FPGAs and mu-Controllers. MSE 2001: 18-19
1990 – 1999
- 1994
- [c2]Lasse Natvig:
Compile and Runtime Padding: An Approach to Realising Synchronous MIMD Execution. IFIP Congress (1) 1994: 553-558 - 1990
- [c1]Lasse Natvig:
Logarithmic time cost optimal parallel sorting is not yet fast in practice!. SC 1990: 486-494
Coauthor Index
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