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"A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator ..."

Hossein Valavi et al. (2018)

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DOI: 10.1109/VLSIC.2018.8502421

access: closed

type: Conference or Workshop Paper

metadata version: 2018-10-30

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  - conf/vlsic/ValaviRNV18
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  - https://dblp.org/rec/conf/vlsic/ValaviRNV18
Hossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma:
A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement. VLSI Circuits 2018: 141-142

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