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"A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC."

Kentaro Yoshioka et al. (2013)

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DOI: 10.1109/ASPDAC.2013.6509581

access: closed

type: Conference or Workshop Paper

metadata version: 2022-12-07

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Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. ASP-DAC 2013: 111-112

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