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"A scalable FPGA-based cerebellum for passage-of-time representation."

Junwen Luo et al. (2014)

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DOI: 10.1109/EMBC.2014.6944279

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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  dblp key:
  - conf/embc/LuoCMYTD14
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  - https://dblp.org/rec/conf/embc/LuoCMYTD14
Junwen Luo, Graeme Coapes, Terrence S. T. Mak, Tadashi Yamazaki, Chung Tin, Patrick Degenaar:
A scalable FPGA-based cerebellum for passage-of-time representation. EMBC 2014: 3102-3105

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