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"DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator ..."

Jacob T. Grycel, Robert J. Walls (2020)

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DOI: 10.1109/ISCAS45731.2020.9181186

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-18

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Jacob T. Grycel, Robert J. Walls:
DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs. ISCAS 2020: 1-5

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