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"Design Considerations for a Sub-25μW PLL with Multi-Phase Output and ..."

Parikha Mehrotra et al. (2021)

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DOI: 10.1109/ISCAS51556.2021.9401212

access: closed

type: Conference or Workshop Paper

metadata version: 2022-12-07

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Parikha Mehrotra, Baibhab Chatterjee, Shovan Maity, Shreyas Sen:
Design Considerations for a Sub-25μW PLL with Multi-Phase Output and 1-450MHz Tuning Range. ISCAS 2021: 1-5

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