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"A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in ..."

Min-Han Hsieh et al. (2012)

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DOI: 10.1109/ISSCC.2012.6176994

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen:
A 6.7MHz-to-1.24GHz 0.0318mm² fast-locking all-digital DLL in 90nm CMOS. ISSCC 2012: 244-246

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