<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<inproceedings key="conf/sigcomm/JiangHXTS23" mdate="2023-09-26">
<author orcid="0009-0008-2842-6392">Jinghui Jiang</author>
<author orcid="0009-0008-1222-7268">Zhenpei Huang</author>
<author orcid="0000-0002-3394-6279">Qiao Xiang</author>
<author orcid="0000-0003-2923-6247">Lu Tang 0004</author>
<author orcid="0000-0002-7362-2789">Jiwu Shu</author>
<title>Poster: P4-DPLL: Accelerating SAT Solving Using Switching ASICs.</title>
<pages>1123-1125</pages>
<year>2023</year>
<booktitle>SIGCOMM</booktitle>
<ee>https://doi.org/10.1145/3603269.3610863</ee>
<crossref>conf/sigcomm/2023</crossref>
<url>db/conf/sigcomm/sigcomm2023.html#JiangHXTS23</url>
</inproceedings></dblp>
