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"A Novel and Efficient Hardware Accelerator Architecture for Signal ..."

Gibin ChackoGeorge et al. (2020)

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DOI: 10.1007/S00034-019-01262-3

access: closed

type: Journal Article

metadata version: 2020-10-06

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  - journals/cssp/ChackoGeorgeMCP20
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  - https://dblp.org/rec/journals/cssp/ChackoGeorgeMCP20
Gibin ChackoGeorge, Abhishek Moitra, Sriyash Caculo, A. Amalin Prince, J. J. U. Buch, Surya K. Pathak:
A Novel and Efficient Hardware Accelerator Architecture for Signal Normalization. Circuits Syst. Signal Process. 39(5): 2425-2441 (2020)

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