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"Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array."

Tadayoshi Enomoto et al. (2008)

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DOI: 10.1093/IETELE/E91-C.4.553

access: closed

type: Journal Article

metadata version: 2020-04-11

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  - journals/ieicet/EnomotoNSH08
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  - https://dblp.org/rec/journals/ieicet/EnomotoNSH08
Tadayoshi Enomoto, Suguru Nagayama, Hiroaki Shikano, Yousuke Hagiwara:
Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array. IEICE Trans. Electron. 91-C(4): 553-561 (2008)

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