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"Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell."

Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto (2014)

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DOI: 10.1587/TRANSFUN.E97.A.1945

access: closed

type: Journal Article

metadata version: 2024-05-07

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  - https://dblp.org/rec/journals/ieicet/YoshimotoKY14
Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(9): 1945-1951 (2014)

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