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"An 8-Bit 0.333-2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS."

Dengquan Li et al. (2015)

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DOI: 10.1142/S0218126615500930

access: closed

type: Journal Article

metadata version: 2020-08-25

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  - journals/jcsc/LiZZY15
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  - https://dblp.org/rec/journals/jcsc/LiZZY15
Dengquan Li, Liang Zhang, Zhangming Zhu, Yintang Yang:
An 8-Bit 0.333-2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS. J. Circuits Syst. Comput. 24(6): 1550093:1-1550093:14 (2015)

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