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"A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 ..."

Bharath Raghavan et al. (2013)

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DOI: 10.1109/JSSC.2013.2279054

access: closed

type: Journal Article

metadata version: 2021-01-21

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  - https://dblp.org/rec/journals/jssc/RaghavanCSMPVHCMC13
Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Deyi Pi, Anand Vasani, Zhi Chao Huang, Burak Çatli, Afshin Momtaz, Jun Cao:
A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS. IEEE J. Solid State Circuits 48(12): 3219-3228 (2013)

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