default search action

combined dblp search
author search
venue search
publication search

ask others

"A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB ..."

Yu-Ping Huang, Yu-Sian Lu, Wei-Zen Chen (2024)

> Home

Details and statistics

DOI: 10.1109/OJCAS.2024.3416397

access: open

type: Journal Article

metadata version: 2024-09-23

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/ojcands/HuangLC24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ojcands/HuangLC24
Yu-Ping Huang, Yu-Sian Lu, Wei-Zen Chen:
A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction. IEEE Open J. Circuits Syst. 5: 291-301 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.