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"A 3-5 GHz, 108fs-RMS jitter, clock receiver circuit for time-interleaved ..."

Kejun Wu et al. (2023)

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DOI: 10.1016/J.MEJO.2023.105889

access: closed

type: Journal Article

metadata version: 2023-09-24

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Kejun Wu, Yangchen Xie, Shubo Tao, Zhong Zhang, Ning Ning, Jing Li, Qi Yu:
A 3-5 GHz, 108fs-RMS jitter, clock receiver circuit for time-interleaved ADCs with a sampling rate of 4 GS/s. Microelectron. J. 139: 105889 (2023)

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