default search action

combined dblp search
author search
venue search
publication search

ask others

"A Branch-&-Bound Test-Access-Mechanism Optimization Method for ..."

Fotis Vartziotis et al. (2017)

> Home

Details and statistics

DOI: 10.1109/TCAD.2017.2664062

access: closed

type: Journal Article

metadata version: 2022-01-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/VartziotisKGC17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/VartziotisKGC17
Fotis Vartziotis, Xrysovalantis Kavousianos, Panagiotis Georgiou, Krishnendu Chakrabarty:
A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-V_dd SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(11): 1911-1924 (2017)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.