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"Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency ..."

Alak Majumder et al. (2019)

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DOI: 10.1109/TCSI.2018.2877571

access: closed

type: Journal Article

metadata version: 2024-10-06

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Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya:
Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1231-1244 (2019)

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