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"Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based ..."

Jin-Fa Lin et al. (2017)

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DOI: 10.1109/TVLSI.2017.2729884

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - journals/tvlsi/LinSHWT17
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  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/LinSHWT17
Jin-Fa Lin, Ming-Hwa Sheu, Yin-Tsung Hwang, Chen-Syuan Wong, Ming-Yan Tsai:
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3033-3044 (2017)

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