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"Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies."

Giuseppe Scotti et al. (2017)

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DOI: 10.1109/TVLSI.2017.2750207

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - journals/tvlsi/ScottiBTP17
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  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/ScottiBTP17
Giuseppe Scotti, Davide Bellizia, Alessandro Trifiletti, Gaetano Palumbo:
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3509-3520 (2017)

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