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"An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain."

Yi Shen et al. (2023)

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DOI: 10.1109/TVLSI.2023.3302842

access: closed

type: Journal Article

metadata version: 2023-10-27

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  - https://dblp.org/rec/journals/tvlsi/ShenHLALDZ23
Yi Shen, Junyan Hao, Shubin Liu, Zeshuai An, Dengquan Li, Ruixue Ding, Zhangming Zhu:
An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1870-1873 (2023)

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