Skip to content
Licensed Unlicensed Requires Authentication Published by De Gruyter Oldenbourg April 5, 2022

A survey of approximate arithmetic circuits and blocks

  • Ke Chen

    Dr. Ke Chen IEEE member, received the B. Sc. degree in Engineering from Huazhong University of Science and Technology (HUST), Wuhan, China, in 2010, and the Ph. D. degree in Computer Engineering from Northeastern University, Boston, in 2020. He is currently an Associate Researcher of College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China. Dr. Chen’s research interests include low-power and high-performance VLSI design, emerging logic and memory devices and circuits, approximate and fault tolerant computing.

    EMAIL logo
    , Peipei Yin

    Peipei Yin received the B. Sc. and M. Sc. degrees from Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 2010 and 2013, respectively. Since Sep. 2015, she has been pursuing the Ph. D. degree in the College of Electronic and Information Engineering, NUAA, Nanjing, China. Her research interests include computer arithmetic, fault tolerance systems, and low power technologies in approximate computing.

    , Weiqiang Liu

    Prof. Weiqiang Liu received the B. Sc. degree in Information Engineering from Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China and the Ph. D. degree in Electronic Engineering from the Queen’s University Belfast (QUB), Belfast, UK, in 2006 and 2012, respectively. In Dec. 2013, he joined the College of Electronic and Information Engineering, NUAA, where he is currently an Associate Professor. He was a Research Fellow in the Institute of Electronics, Communications and Information Technology (ECIT) at QUB from Aug. 2012 to Nov. 2013. He serves as an Associate Editor of IEEE Transactions on Computers (TC), the leader of The Multimedia Team at TC Editorial Board, the Guest Editors of two special issues of IEEE Transactions on Emerging Topics in Computing. He has been a technical program committee member for several international conferences including the IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Symposium on Computer Arithmetic (ARITH), the Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) and the International Conference on Neural Information Processing (ICONIP). He has published one research book by Artech House and over 40 leading journal and conference papers. His paper was finalist in the Best Paper Contest of ISCAS 2011 and he is the co-author of a Best Paper Candidate of GLSVLSI 2015. His research interests include computer arithmetic, emerging technologies in computing systems, and cryptographic hardware. He is a Senior Member of IEEE.

    and Fabrizio Lombardi

    Prof. Fabrizio Lombardi graduated in 1977 from the University of Essex (UK) with a B. Sc. (Hons.) in Electronic Engineering. In 1977 he joined the Microwave Research Unit at University College London, where he received the Master in Microwaves and Modern Optics (1978), the Diploma in Microwave Engineering (1978) and the Ph. D. from the University of London (1982). He is currently the holder of the International Test Conference (ITC) Endowed Chair Professorship at Northeastern University, Boston. During 2007–2010 Dr. Lombardi was the Editor-In-Chief of the IEEE Transactions on Computers. Currently, he is the Editor-in-Chief of the IEEE Transactions on Nanotechnology and the inaugural Editor-in-Chief of the IEEE Transactions on Emerging Topics in Computing. He currently serves as an elected Member of the Board of Governors of the IEEE Computer Society. His research interests are bio-inspired and nano manufacturing/computing, VLSI design, testing, and fault/defect tolerance of digital systems. He has extensively published in these areas and coauthored/edited seven books. He is a Fellow of IEEE.

Abstract

Approximate computing has become an emerging research topic for energy-efficient design of circuits and systems. Many approximate arithmetic circuits have been proposed, therefore it is critical to summarize the available approximation techniques to improve performance and energy efficiency at a acceptable accuracy loss. This paper presents an overview of circuit-level techniques used for approximate arithmetic. This paper provides a detailed review of circuit-level approximation techniques for the arithmetic data path. Its focus is on identifying critical circuit-level approximation techniques that apply to computational units and blocks. Approximate adders, multipliers, dividers, and squarer are introduced and classified according to their approximation methods. FFT and MAC are discussed as computational blocks that employ an approximate algorithm for implementation.

ACM CCS:

About the authors

Dr. Ke Chen

Dr. Ke Chen IEEE member, received the B. Sc. degree in Engineering from Huazhong University of Science and Technology (HUST), Wuhan, China, in 2010, and the Ph. D. degree in Computer Engineering from Northeastern University, Boston, in 2020. He is currently an Associate Researcher of College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China. Dr. Chen’s research interests include low-power and high-performance VLSI design, emerging logic and memory devices and circuits, approximate and fault tolerant computing.

Peipei Yin

Peipei Yin received the B. Sc. and M. Sc. degrees from Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China, in 2010 and 2013, respectively. Since Sep. 2015, she has been pursuing the Ph. D. degree in the College of Electronic and Information Engineering, NUAA, Nanjing, China. Her research interests include computer arithmetic, fault tolerance systems, and low power technologies in approximate computing.

Prof. Weiqiang Liu

Prof. Weiqiang Liu received the B. Sc. degree in Information Engineering from Nanjing University of Aeronautics and Astronautics (NUAA), Nanjing, China and the Ph. D. degree in Electronic Engineering from the Queen’s University Belfast (QUB), Belfast, UK, in 2006 and 2012, respectively. In Dec. 2013, he joined the College of Electronic and Information Engineering, NUAA, where he is currently an Associate Professor. He was a Research Fellow in the Institute of Electronics, Communications and Information Technology (ECIT) at QUB from Aug. 2012 to Nov. 2013. He serves as an Associate Editor of IEEE Transactions on Computers (TC), the leader of The Multimedia Team at TC Editorial Board, the Guest Editors of two special issues of IEEE Transactions on Emerging Topics in Computing. He has been a technical program committee member for several international conferences including the IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Symposium on Computer Arithmetic (ARITH), the Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) and the International Conference on Neural Information Processing (ICONIP). He has published one research book by Artech House and over 40 leading journal and conference papers. His paper was finalist in the Best Paper Contest of ISCAS 2011 and he is the co-author of a Best Paper Candidate of GLSVLSI 2015. His research interests include computer arithmetic, emerging technologies in computing systems, and cryptographic hardware. He is a Senior Member of IEEE.

Prof. Fabrizio Lombardi

Prof. Fabrizio Lombardi graduated in 1977 from the University of Essex (UK) with a B. Sc. (Hons.) in Electronic Engineering. In 1977 he joined the Microwave Research Unit at University College London, where he received the Master in Microwaves and Modern Optics (1978), the Diploma in Microwave Engineering (1978) and the Ph. D. from the University of London (1982). He is currently the holder of the International Test Conference (ITC) Endowed Chair Professorship at Northeastern University, Boston. During 2007–2010 Dr. Lombardi was the Editor-In-Chief of the IEEE Transactions on Computers. Currently, he is the Editor-in-Chief of the IEEE Transactions on Nanotechnology and the inaugural Editor-in-Chief of the IEEE Transactions on Emerging Topics in Computing. He currently serves as an elected Member of the Board of Governors of the IEEE Computer Society. His research interests are bio-inspired and nano manufacturing/computing, VLSI design, testing, and fault/defect tolerance of digital systems. He has extensively published in these areas and coauthored/edited seven books. He is a Fellow of IEEE.

References

1. W. Liu, F. Lombardi, and M. Shulte, A Retrospective and Prospective View of Approximate Computing {Point of View}, Proceedings of the IEEE, vol. 108, no. 3, pp. 394–399, March 2020, doi: 10.1109/JPROC.2020.2975695.Search in Google Scholar

2. S. Misailovic, S. Sidiroglou, H. Hoffmann, and M. Rinard, Quality of service profiling, in Proceedings of the 32nd ACM/IEEE International Conference on Software Engineering-Volume 1, 2010, pp. 25–34.10.1145/1806799.1806808Search in Google Scholar

3. H. Hoffmann, S. Misailovic, S. Sidiroglou, A. Agarwal, and M. Rinard, Using code perforation to improve performance, reduce energy consumption, and respond to failures, 2009.Search in Google Scholar

4. M. Samadi, D. A. Jamshidi, J. Lee, and S. Mahlke, Paraprox: Pattern-based approximation for data parallel applications, in Proceedings of the 19th international conference on Architectural support for programming languages and operating systems, 2014, pp. 35–50.10.1145/2541940.2541948Search in Google Scholar

5. N. Goodman, V. Mansinghka, D. M. Roy, K. Bonawitz, and J. B. Tenenbaum, Church: a language for generative models, arXiv preprint arXiv:1206.3255, 2012.Search in Google Scholar

6. T. Yeh, P. Faloutsos, M. Ercegovac, S. Patel, and G. Reinman, The art of deception: Adaptive precision reduction for area efficient physics acceleration, in 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007), 2007, pp. 394–406.10.1109/MICRO.2007.9Search in Google Scholar

7. H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger, Neural acceleration for general-purpose approximate programs, in 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012, pp. 449–460.10.1109/MICRO.2012.48Search in Google Scholar

8. A. Sampson, W. Dietl, E. Fortuna, D. Gnanapragasam, L. Ceze, and D. Grossman, EnerJ: Approximate data types for safe and general low-power computation, ACM SIGPLAN Notices, vol. 46, no. 6, pp. 164–174, 2011.10.1145/1993498.1993518Search in Google Scholar

9. Y. Fang, H. Li, and X. Li, SoftPCM: Enhancing energy efficiency and lifetime of phase change memory in video applications via approximate write, in 2012 IEEE 21st Asian Test Symposium, 2012, pp. 131–136.10.1109/ATS.2012.57Search in Google Scholar

10. A. Sampson, J. Nelson, K. Strauss, and L. Ceze, Approximate storage in solid-state memories, ACM Transactions on Computer Systems (TOCS), vol. 32, no. 3, pp. 1–23, 2014.10.1145/2540708.2540712Search in Google Scholar

11. M. R. Choudhury and K. Mohanram, Approximate logic circuits for low overhead, non-intrusive concurrent error detection, in Proceedings of the conference on Design, automation and test in Europe, 2008, pp. 903–908.10.1145/1403375.1403593Search in Google Scholar

12. D. Mohapatra, V. K. Chippa, A. Raghunathan, and K. Roy, Design of voltage-scalable meta-functions for approximate computing, in 2011 Design, Automation & Test in Europe, 2011, pp. 1–6.10.1109/DATE.2011.5763154Search in Google Scholar

13. R. Ye, T. Wang, F. Yuan, R. Kumar, and Q. Xu, On reconfiguration-oriented approximate adder design and its application, in 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013, pp. 48–54.10.1109/ICCAD.2013.6691096Search in Google Scholar

14. N. Zhu, W. L. Goh, W. Zhang, K. S. Yeo, and Z. H. Kong, Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing, IEEE transactions on very large scale integration (VLSI) systems, vol. 18, no. 8, pp. 1225–1229, 2009.10.1109/TVLSI.2009.2020591Search in Google Scholar

15. S. Hashemi, R. I. Bahar, and S. Reda, DRUM: A dynamic range unbiased multiplier for approximate applications, in 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015, pp. 418–425.10.1109/ICCAD.2015.7372600Search in Google Scholar

16. M. Imani, D. Peroni, and T. Rosing, CFPU: Configurable floating point multiplier for energy-efficient computing, in 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, pp. 1–6.10.1145/3061639.3062210Search in Google Scholar

17. J. Liang, J. Han, and F. Lombardi, New Metrics for the Reliability of Approximate and Probabilistic Adders, IEEE Transactions on Computers, vol. 62, no. 9, pp. 1760–1771, Sept. 2013, doi: 10.1109/TC.2012.146.Search in Google Scholar

18. S. Amanollahi, M. Kamal, A. Afzali-Kusha, and M. Pedram, Circuit-Level Techniques for Logic and Memory Blocks in Approximate Computing Systemsx, Proceedings of the IEEE, vol. 108, no. 12, pp. 2150–2177, Dec. 2020, doi: 10.1109/JPROC.2020.3020792.Search in Google Scholar

19. H. Jiang, F. J. H. Santiago, H. Mo, L. Liu, and J. Han, Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications, Proceedings of the IEEE, vol. 108, no. 12, pp. 2108–2135, Dec. 2020, doi: 10.1109/JPROC.2020.3006451.Search in Google Scholar

20. H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas, Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 4, pp. 850–862, 2009.10.1109/TCSI.2009.2027626Search in Google Scholar

21. J. Lee, H. Seo, H. Seok, and Y. Kim, A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation, IEEE Access, vol. 9, pp. 119939–119953, 2021, doi: 10.1109/ACCESS.2021.3108443.Search in Google Scholar

22. W. Ahmad, B. Ayrancioglu, and I. Hamzaoglu, Low Error Efficient Approximate Adders for FPGAs, IEEE Access, vol. 9, pp. 117232–117243, 2021, doi: 10.1109/ACCESS.2021.3107370.Search in Google Scholar

23. P. Kulkarni, P. Gupta, and M. Ercegovac, Trading accuracy for power with an underdesigned multiplier architecture, in 2011 24th International Conference on VLSI Design, 2011, pp. 346–351.10.1109/VLSID.2011.51Search in Google Scholar

24. W. Liu, L. Qian, C. Wang, H. Jiang, J. Han, and F. Lombardi, Design of approximate radix-4 booth multipliers for error-tolerant computing, IEEE Transactions on Computers, vol. 66, no. 8, pp. 1435–1441, 2017.10.1109/TC.2017.2672976Search in Google Scholar

25. Y. He, X. Yi, B. Ma, Z. Zhang, and B. Zhang, A Probabilistic Prediction Based Fixed-Width Booth Multiplier, in 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018, pp. 321–324, doi: 10.1109/APCCAS.2018.8605690.10.1109/APCCAS.2018.8605690Search in Google Scholar

26. K. Y. Kyaw, W. L. Goh, and K. S. Yeo, Low-power high-speed multiplier for error-tolerant application, in 2010 IEEE international conference of electron devices and solid-state circuits (EDSSC), 2010, pp. 1–4.Search in Google Scholar

27. S. Narayanamoorthy, H. A. Moghaddam, Z. Liu, T. Park, and N. S. Kim, Energy-efficient approximate multiplication for digital signal processing and classification applications, IEEE transactions on very large scale integration (VLSI) systems, vol. 23, no. 6, pp. 1180–1184, 2014.10.1109/TVLSI.2014.2333366Search in Google Scholar

28. C.-H. Lin and C. Lin, High accuracy approximate multiplier with error correction, in 2013 IEEE 31st International Conference on Computer Design (ICCD), 2013, pp. 33–38.10.1109/ICCD.2013.6657022Search in Google Scholar

29. D. Baran, M. Aktan, and V. G. Oklobdzija, Energy efficient implementation of parallel CMOS multipliers with improved compressors, in Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, 2010, pp. 147–152.10.1145/1840845.1840876Search in Google Scholar

30. A. Momeni, J. Han, P. Montuschi, and F. Lombardi, Design and analysis of approximate compressors for multiplication, IEEE Transactions on Computers, vol. 64, no. 4, pp. 984–994, 2014.10.1109/TC.2014.2308214Search in Google Scholar

31. C. Liu, J. Han, and F. Lombardi, A low-power, high-performance approximate multiplier with configurable partial error recovery, in 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, pp. 1–4.10.7873/DATE.2014.108Search in Google Scholar

32. C. Liu, Design and analysis of approximate adders and multipliers, Master Thesis, University of Alberta, Canada, 2014.Search in Google Scholar

33. M. Ahmadinejad, M. H. Moaiyeri, and F. Sabetzadeh, Energy and area efficient imprecise compressors for approximate multiplication at nanoscale, AEU-Int. J. Electron. Commun., vol. 110, Oct. 2019, Art. no. 152859.10.1016/j.aeue.2019.152859Search in Google Scholar

34. A. G. M. Strollo, E. Napoli, D. De Caro, N. Petra, and G. D. Meo, Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9, pp. 3021–3034, Sept. 2020, doi: 10.1109/TCSI.2020.2988353.Search in Google Scholar

35. L. Chen, J. Han, W. Liu, and F. Lombardi, Design of Approximate Unsigned Integer Non-Restoring Divider for Inexact Computing, in Proceedings of the 25th Edition on Great Lakes Symposium on VLSI, 2015, pp. 51–56. doi: 10.1145/2742060.2742063.Search in Google Scholar

36. L. Chen, J. Han, W. Liu, and F. Lombardi, On the Design of Approximate Restoring Dividers for Error-Tolerant Applications, IEEE Transactions on Computers, vol. 65, no. 8, pp. 2522–2533, 1 Aug. 2016, doi: 10.1109/TC.2015.2494005.Search in Google Scholar

37. R. Zendegani, M. Kamal, A. Fayyazi, A. Afzali-Kusha, S. Safari, and M. Pedram, SEERAD: A high speed yet energy-efficient rounding-based approximate divider, in 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 1481–1484.10.3850/9783981537079_0521Search in Google Scholar

38. M. Vaeztourshizi, M. Kamal, A. Afzali-Kusha, and M. Pedram, An Energy-Efficient, Yet Highly-Accurate, Approximate Non-Iterative Divider, 2018, doi: 10.1145/3218603. 3218650.10.1145/3218603Search in Google Scholar

39. S. Vahdat, M. Kamal, A. Afzali-Kusha, M. Pedram, and Z. Navabi, TruncApp: A truncation-based approximate divider for energy efficient DSP applications, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, pp. 1635–1638, doi: 10.23919/DATE.2017.7927254.Search in Google Scholar

40. S. Venkataramani, S. T. Chakradhar, K. Roy, and A. Raghunathan, Approximate computing and the quest for computing efficiency, in 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, pp. 1–6, doi: 10.1145/2744769.2744904.Search in Google Scholar

41. H. Jiang, L. Liu, F. Lombardi, and J. Han, Adaptive approximation in arithmetic circuits: A low-power unsigned divider design, in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, pp. 1411–1416, doi: 10.23919/DATE.2018.8342233.Search in Google Scholar

42. A. Deshpande and J. Draper, Squaring units and a comparison with multipliers, in 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 2010, pp. 1266–1269, doi: 10.1109/MWSCAS.2010.5548763.Search in Google Scholar

43. A. Avramović, Z. Babić, D. Raič, D. Strle, and P. Bulić, An approximate logarithmic squaring circuit with error compensation for DSP applications, Microelectronics Journal, vol. 45, no. 3, pp. 263–271, 2014.10.1016/j.mejo.2014.01.005Search in Google Scholar

44. N. Petra, D. De Caro, V. Garofalo, E. Napoli, and A. G. Strollo, Truncated squarer with minimum mean-square error, Microelectronics Journal, vol. 45, no. 6, pp. 799–804, 2014.10.1016/j.mejo.2014.02.018Search in Google Scholar

45. S. R. Datla, M. A. Thornton, and D. W. Matula, A low power high performance Radix-4 approximate squaring circuit, in Proc. 20th IEEE International Conference on Application-specific Systems, Architectures and Processors. IEEE, pp. 91–97, 2009.10.1109/ASAP.2009.35Search in Google Scholar

46. K.-J. Cho and J.-G. Chung, Low error fixed-width two’s complement squarer design using Booth-folding technique, IET Computers & Digital Techniques, vol. 1, no. 4, pp. 414–422, 2007.10.1049/iet-cdt:20060033Search in Google Scholar

47. Y.-H. Chen, Area-efficient fixed-width squarer with dynamic error-compensation circuit, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 9, pp. 851–855, 2015.10.1109/TCSII.2015.2435752Search in Google Scholar

48. K. M. Reddy, M. Vasantha, Y. N. Kumar, and D. Dwivedi, Design of approximate Booth squarer for error-tolerant computing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 5, pp. 1230–1241, 2020.10.1109/TVLSI.2020.2976131Search in Google Scholar

49. J. Du, K. Chen, P. Yin, C. Yan, and W. Liu, Design of An Approximate FFT Processor Based on Approximate Complex Multipliers, in 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021, pp. 308–313, doi: 10.1109/ISVLSI51109.2021.00063.Search in Google Scholar

50. B. Liu et al., Precision Adaptive MFCC Based on R2SDF-FFT and Approximate Computing for Low-Power Speech Keywords Recognition, IEEE Circuits and Systems Magazine, vol. 21, no. 4, pp. 24–39, Fourthquarter 2021, doi: 10.1109/MCAS.2021.3118175.Search in Google Scholar

51. W. Liu, Q. Liao, F. Qiao, W. Xia, C. Wang, and F. Lombardi, Approximate designs for fast Fourier transform (FFT) with application to speech recognition, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 12, pp. 4727–4739, 2019.10.1109/TCSI.2019.2933321Search in Google Scholar

52. L. Cai, Y. Qian, Y. He, and W. Feng, Design of Approximate Multiplierless DCT with CSD Encoding for Image Processing, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1–4.10.1109/ISCAS51556.2021.9401200Search in Google Scholar

53. J. Emer, V. Sze, Y.-H. Chen, and T.-J. Yang, Hardware architectures for deep neural networks, CICS/MTL Tutorial, vol. 27, p. 258, Mar. 2017.Search in Google Scholar

54. D. Esposito, A. G. M. Strollo, and M. Alioto, Low-power approximate MAC unit, in 2017 13th Conference on Ph. D. Research in Microelectronics and Electronics (PRIME), 2017, pp. 81–84.10.1109/PRIME.2017.7974112Search in Google Scholar

55. G. A. Gillani, M. A. Hanif, B. Verstoep, S. H. Gerez, M. Shafique, and A. B. J. Kokkeler, MACISH: Designing approximate MAC accelerators with internal-self-healing, IEEE Access, vol. 7, pp. 77142–77160, 2019.10.1109/ACCESS.2019.2920335Search in Google Scholar

56. E. Adams, S. Venkatachalam, and S.-B. Ko, Energy-efficient approximate MAC unit, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, pp. 1–4.10.1109/ISCAS.2019.8701880Search in Google Scholar

57. T. Yang, T. Sato, and T. Ukezono, An approximate multiply-accumulate unit with low power and reduced area, in 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019, pp. 385–390.10.1109/ISVLSI.2019.00076Search in Google Scholar

58. D. Esposito, D. de Caro, E. Napoli, N. Petra, and A. G. M. Strollo, On the use of approximate adders in carry-save multiplier-accumulators, in 2017 IEEE international symposium on circuits and systems (ISCAS), 2017, pp. 1–4.10.1109/ISCAS.2017.8050437Search in Google Scholar

59. P. Yin, C. Wang, H. Waris, W. Liu, Y. Han, and F. Lombardi, Design and analysis of energy-efficient dynamic range approximate logarithmic multipliers for machine learning, IEEE Transactions on Sustainable Computing, 2020.10.1109/TSUSC.2020.3004980Search in Google Scholar

60. G. Park, J. Kung, and Y. Lee, Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC Operator, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 7, pp. 2950–2961, July 2021, doi: 10.1109/TCSI.2021.3073177.Search in Google Scholar

61. R. Wang, X. Fan, Q. Li, H. Liu, and S. Lu, AL-MAC: Adaptive Error Compensation Approximate MAC, in 2021 4th International Conference on Circuits, Systems and Simulation (ICCSS), 2021, pp. 56–61, doi: 10.1109/ICCSS51193.2021.9464180.Search in Google Scholar

Received: 2021-10-25
Revised: 2022-02-23
Accepted: 2022-02-24
Published Online: 2022-04-05
Published in Print: 2022-06-27

© 2022 Walter de Gruyter GmbH, Berlin/Boston

Downloaded on 20.1.2025 from https://www.degruyter.com/document/doi/10.1515/itit-2021-0055/html
Scroll to top button