Abstract:
This paper presents a two's complement high-speed twin-pipe serial/parallel multiplier architecture which produces y=cd, where c is the parallel coefficient and d is the ...Show MoreMetadata
Abstract:
This paper presents a two's complement high-speed twin-pipe serial/parallel multiplier architecture which produces y=cd, where c is the parallel coefficient and d is the serial data. The multiplier is based on the twin pipeline (twin-pipe) concept, in which two data bits are processed each clock cycle. The high serial data throughput rate is mainly due to the use of: 1) a novel twin-pipe architecture, 2) new twin-pipe adder types, and 3) a new multiplier circuit structure. A 4-bit high-speed twin-pipe serial/parallel multiplier, on an active area of 0.224 mm/sup 2/, has been designed and fabricated in a 1.0-/spl mu/m N-well double-metal single-poly CMOS process. Testing of the multiplier shows that the maximal serial data throughput rate is 965 Mb/s at V/sub dd/=5 V.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 31, Issue: 2, February 1996)
DOI: 10.1109/4.488000