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A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture | IEEE Journals & Magazine | IEEE Xplore

A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture


Abstract:

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference freque...Show More

Abstract:

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-/spl mu/m CMOS technology is used to fabricate the chip.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 31, Issue: 4, April 1996)
Page(s): 487 - 493
Date of Publication: 06 August 2002

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