Abstract:
A 16*16 bit multiplier integrated circuit fabricated in a CMOS technology having only one level of metallization is described. Microarchitecture for the multiplier has be...Show MoreMetadata
Abstract:
A 16*16 bit multiplier integrated circuit fabricated in a CMOS technology having only one level of metallization is described. Microarchitecture for the multiplier has been optimized to balance the delays in different sections of the chip. A typical multiplication time of 6.75 ns at 3.3 V power supply has been measured, and better results are expected from a process optimized for 0.5 mu m devices.<>
Published in: IEEE Journal of Solid-State Circuits ( Volume: 24, Issue: 4, August 1989)
DOI: 10.1109/4.34072