A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology | IEEE Journals & Magazine | IEEE Xplore

A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology


Abstract:

A 16*16 bit multiplier integrated circuit fabricated in a CMOS technology having only one level of metallization is described. Microarchitecture for the multiplier has be...Show More

Abstract:

A 16*16 bit multiplier integrated circuit fabricated in a CMOS technology having only one level of metallization is described. Microarchitecture for the multiplier has been optimized to balance the delays in different sections of the chip. A typical multiplication time of 6.75 ns at 3.3 V power supply has been measured, and better results are expected from a process optimized for 0.5 mu m devices.<>
Published in: IEEE Journal of Solid-State Circuits ( Volume: 24, Issue: 4, August 1989)
Page(s): 922 - 927
Date of Publication: 31 August 1989

ISSN Information:


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