A new FFT architecture and chip design for motion compensation based on phase correlation | IEEE Conference Publication | IEEE Xplore

A new FFT architecture and chip design for motion compensation based on phase correlation


Abstract:

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 /spl mu/m CMOS technology and can ...Show More

Abstract:

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 /spl mu/m CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8/spl times/8 mm/sup 2/ and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.
Date of Conference: 19-21 August 1996
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-8186-7542-X
Print ISSN: 2160-0511
Conference Location: Chicago, IL, USA

References

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