Abstract:
Test generation for synchronous sequential circuits can be facilitated by decomposing the circuit into a cycle free interconnection of submachines, such that all feedback...Show MoreMetadata
Abstract:
Test generation for synchronous sequential circuits can be facilitated by decomposing the circuit into a cycle free interconnection of submachines, such that all feedback loops are included within the submachines. In this work, we describe a test generation procedure that takes advantage of cycle free circuit decomposition. The paper focuses on one of the subproblems of the test generation problem, the output sequence justification problem. We propose a solution to this problem and show how it can be incorporated into a test generation procedure.
Published in: Proceedings ED&TC European Design and Test Conference
Date of Conference: 11-14 March 1996
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-8186-7424-5
Print ISSN: 1066-1409