Abstract:
Program behavior studies demonstrate that a significant fraction of load instructions in a program read the data stored by an instruction in the immediate past. In this p...Show MoreMetadata
Abstract:
Program behavior studies demonstrate that a significant fraction of load instructions in a program read the data stored by an instruction in the immediate past. In this paper, we propose a scheme entitled the Code Coalescing Unit that eliminates several of the memory access instructions by buffering the data in a Store Register Rename Buffer (SRRB) which is similar to the store buffer and renaming the instructions that use the data to access it directly from the buffer. The Code Coalescing Unit (CCU) can be considered as an extension to the fill unit proposed by S.W. Melvin et al. (1988). Their fill unit groups together micro-operations into larger atomic units and stores them into the decoded instruction cache (DIC) which are later executed directly from the DIC. The original fill unit grouped together micro-operations into larger atomic units, but the proposed Code Coalescing Unit goes further by eliminating particular load operations in the process of grouping together micro-operations. Experiments on eight applications including Microsoft Word for Windows, Microsoft C++ compiler and two SPEC programs demonstrate that approximately 25%, 34% or 42% of all load operations performed by these applications could have been eliminated using a Code Coalescing Unit in conjunction with a Store Register Rename Buffer of 8, 16 or 32 entries respectively.
Published in: Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)
Date of Conference: 05-07 October 1998
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-8186-9099-2
Print ISSN: 1063-6404