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Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor | IEEE Journals & Magazine | IEEE Xplore

Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor


Abstract:

This column features retrospectives from the authors of six MICRO Test of Time award-winning papers: "MIPS: A Microprocessor Architecture" by Norman Jouppi and colleagues...Show More

Abstract:

This column features retrospectives from the authors of six MICRO Test of Time award-winning papers: "MIPS: A Microprocessor Architecture" by Norman Jouppi and colleagues; "HPS, A New Microarchitecture: Rationale and Introduction" by Yale Patt, Wen-Mei Hwu, and Mike Shebanow; "Critical Issues Regarding HPS, A High Performance Microarchitecture" by Yale Patt and colleagues; "Hardware Support for Large Atomic Units in Dynamically Scheduled Machines" by Steve Melvin, Mike Shebanow, and Yale Patt; "Two-Level Adaptive Training Branch Prediction" by Tse-Yu Yeh and Yale Patt; and "Executing Compressed Programs on an Embedded RISC Architecture" by Andy Wolfe and Alex Chanin.
Published in: IEEE Micro ( Volume: 36, Issue: 4, July-Aug. 2016)
Page(s): 70 - 85
Date of Publication: 12 August 2016

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