Accelerating the Accelerator Memory Interface with Access-Execute and Dataflow | IEEE Journals & Magazine | IEEE Xplore

Accelerating the Accelerator Memory Interface with Access-Execute and Dataflow


Abstract:

The Memory Access Dataflow execution model and hardware architecture combine principles of decoupled access and execution, dataflow computation, and event-condition-actio...Show More

Abstract:

The Memory Access Dataflow execution model and hardware architecture combine principles of decoupled access and execution, dataflow computation, and event-condition-action rules to redevelop the main primitives of an out-of-order core in a power-efficient way that targets memory accesses that naturally occur in programs or get induced when some work is offloaded to an accelerator. Such a mechanism can allow in-core accelerators to integrate with high- or low-performance cores without compromising performance, run at low power by turning off the core during such phases, and provide high energy savings.
Published in: IEEE Micro ( Volume: 36, Issue: 3, May-June 2016)
Page(s): 31 - 41
Date of Publication: 25 May 2016

ISSN Information:


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