Global Load Instruction Aggregation Based on Array Dimensions | IEEE Conference Publication | IEEE Xplore

Global Load Instruction Aggregation Based on Array Dimensions


Abstract:

Most modern processors have some cache memoriesthat are much faster than a main memory, and it isimportant to utilize them effectively for efficient programexecution. The...Show More

Abstract:

Most modern processors have some cache memoriesthat are much faster than a main memory, and it isimportant to utilize them effectively for efficient programexecution. The cache memories function well if temporal or spatial localities in the program are enhanced. Therefore, the cache efficiency can be improved by making accesses to the same array continuous. In addition, a multidimensional array can be regarded as an array of lower dimensional arrays, which means that it is more effective to continuously aggregate the array references with same indexes more in thehighest dimensions, even if they are not completely same. Wepropose a new cache optimization technique for improvingcache efficiency based on global code motion. Our techniquemoves a load instruction to immediately after the precedingload instructions accessing the same array with the most similarindexes, and then delays it as late as possible without changingthe access order. These two-step code motions contribute tonot only the improvement of the cache efficiency in the entireprogram but also the suppression of register pressure. Wehave implemented our technique in a real compiler and haveevaluated it for SPEC benchmarks. The experimental resultsshow that our technique can decrease cache misses by about99.9% in the best case.
Date of Conference: 13-15 July 2014
Date Added to IEEE Xplore: 07 October 2014
ISBN Information:

ISSN Information:

Conference Location: Beijing, China

References

References is not available for this document.