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Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories

Published: 10 May 2017 Publication History

Abstract

The vulnerability of VLSI designs to soft errors grows with technology scaling. In order to allow a cost-effective reliability aware design process, it is critical to assess soft error reliability parameters in early design stages. This paper presents a new methodology to estimate digital circuit vulnerability to soft errors of circuits described at Register Transfer Level (RTL). Single Event Upsets (SEUs) propagation through RTL bit-vector operations is modeled and analyzed based on Satisfiability Modulo Theories (SMT). For instance, the bit-vector reduction operators and arithmetic operators were modeled using SMT to include their fault propagation properties. In order to illustrate the practical utilization of our work, we have analyzed different RTL combinational circuits. Experimental results demonstrate that the proposed framework is on average about 4 times faster than other comparable contemporary techniques. Moreover, it provides more accurate and detailed results of the circuit vulnerability allowing a more efficient applicability of fault tolerance techniques.

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Cited By

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  • (2022)Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computingInternational Journal of Intelligent Systems10.1002/int.2294037:11(8309-8326)Online publication date: 26-Sep-2022

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cover image ACM Conferences
GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017
May 2017
516 pages
ISBN:9781450349727
DOI:10.1145/3060403
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 10 May 2017

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Author Tags

  1. register transfer level (rtl)
  2. satisfiability modulo theories (smt)
  3. single event upset (seu)
  4. soft error rate (ser)

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  • Research-article

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  • Natural Sciences and Engineering Research Council of Canada (NSERC)

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GLSVLSI '17
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GLSVLSI '17: Great Lakes Symposium on VLSI 2017
May 10 - 12, 2017
Alberta, Banff, Canada

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GLSVLSI '17 Paper Acceptance Rate 48 of 197 submissions, 24%;
Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2022)Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computingInternational Journal of Intelligent Systems10.1002/int.2294037:11(8309-8326)Online publication date: 26-Sep-2022

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