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Dynamic Partitioned Scheduling of Real-Time DAG Tasks on ARM big.LITTLE Architectures*
This paper evaluates the combination of a Directed Acyclic Graph (DAG) task splitting technique already proposed in the literature and the state-of-the-art, energy-aware version of the well-known CBS server (BL-CBS), which dynamically partitions and ...
Heterogeneous multicore SDRAM interference analysis
- Alfonso Mascareñas González,
- Frédéric Boniol,
- Youcef Bouchebaba,
- Jean-Loup Bussenot,
- Jean-Baptiste Chaudron
The purpose of this paper is to describe a set of DDR3 SDRAM interference estimation cost functions. The arbitration system of the SDRAM controller heavily impact the interference analysis. In this work, three arbitration are considered, corresponding ...
Exploring AMD GPU Scheduling Details by Experimenting With “Worst Practices”
Graphics processing units (GPUs) have been the target of a significant body of recent real-time research, but research is often hampered by the “black box” nature of GPU hardware and software. Now that one GPU manufacturer, AMD, has embraced an open-...
Towards Virtualization-Agnostic Latency for Time-Sensitive Applications
As time-sensitive applications are deployed spanning multiple edge clouds, delivering consistent and scalable latency performance across different virtualized hosts becomes increasingly challenging. In contrast to traditional real-time systems requiring ...
On the Defectiveness of SCHED_DEADLINE w.r.t. Tardiness and Affinities, and a Partial Fix
SCHED_DEADLINE (DL for short) is an Earliest-Deadline-First (EDF) scheduler included in the Linux kernel. A question motivated by DL is how EDF should be implemented in the presence of CPU affinities to maintain optimal bounded tardiness guarantees. ...
Formal Verification of a Mixed-Trust Synchronization Protocol
- Ruben Martins,
- Michael McCall,
- Dionisio de Niz,
- Amit Vasudevan,
- Bjorn Andersson,
- Mark Klein,
- John P. Lehoczky,
- Hyoseung Kim
Cyber-Physical Systems (CPS) are becoming widespread in many safety-critical real-time applications, such as autonomous driving, robotics systems, and unmanned aircraft. However, verifying these complex real-time systems remains an open challenge ...
Synthesising Schedules to Improve QoS of Best-effort Traffic in TSN Networks
The IEEE Time-Sensitive Networking (TSN) standards’ amendment 802.1Qbv provides real-time guarantees for Scheduled Traffic (ST) streams by the Time Aware Shaper (TAS) mechanism. In this paper, we develop offline schedule optimization objective ...
A model-based approach for analysing network communication timeliness in IMA systems at concept level
Analyzing the resource adequacy of complex cyber-physical systems at concept development stage can be a challenging task since there are a lot of uncertainties about the system at this stage. In Integrated Modular Avionics (IMA) systems, with a life-...
Improvements to Deep-Learning-based Feasibility Prediction of Switched Ethernet Network Configurations
Graph neural network (GNN) is an advanced machine learning model, which has been recently applied to encode Ethernet configurations as graphs and predict their feasibility in terms of meeting deadlines constraints. Ensembles of GNN models have proven to ...
How to Optimize Joint Routing and Scheduling Models for TSN Using Integer Linear Programming
Reliable real-time communication is an essential technology for industrial manufacturing but also other branches to transport mission-critical messages. IEEE Time-Sensitive Networking (TSN) is a disruptive real-time communication standard extending ...
Data Cache Analysis by Counting Integer Points
The scheduling of reliable real-time systems require a precise and sound analysis of the execution times of their tasks. Part of these execution times is spent fetching data from the main memory to the cache memories. These fetch events occur on cache ...
Bus-Contention Aware Schedulability Analysis for the 3-Phase Task Model with Partitioned Scheduling
Multicore platforms are being increasingly adopted in Cyber -Physical Systems (CPS) due to their advantages over single-core processors, such as raw computing power and energy efficiency. Typically, multicore platforms use a shared system bus that ...
Precise Scheduling of Mixed-Criticality Tasks on Varying-Speed Multiprocessors
In conventional real-time systems analysis, each system parameter is specified by a single estimate, which must pessimistically cover the worst case. Mixed-criticality (MC) design has been proposed to mitigate such pessimism by providing a single system ...
An Efficient Proactive Thermal-Aware Scheduler for DVFS-enabled Single-Core Processors
For decades now, thermal rise has been spotted as one of the major constraints of performance for high-end safety-critical processors. In this context, Dynamic Voltage and Frequency Scaling () based solutions have proven to be effective to manage the ...
Migrating Constant Bandwidth Servers on Multi-Cores
This paper introduces a novel admission test for partitioned CBS reservations on multi-core systems, that, on a new reservation arrival, is capable of exploiting better the CPU capacity in cases in which tasks have just recently left the CPU (for ...
Feasibility Analysis of Conditional DAG Tasks is co-NPNP-Hard
Feasibility-analysis algorithms have traditionally been required to have running times no worse than pseudo-polynomial in their inputs, in order to be considered efficient. But this is changing: motivated by a vast improvement in the performance of ...
Response Time Analysis of Parallel Real-Time DAG Tasks Scheduled by Thread Pools
Modern high-end embedded systems nowadays have to process enormous amounts of data. In order to speed up the computations and fully exploit the resources of the underlying hardware architectures, software developers can avail parallelism frameworks ...
Optimal Synthesis of IDK-Cascades
A classifier is a software component, often based upon deep learning (DL), that categorizes each input provided to it into one of a fixed set of “classes”. An IDK classifier may additionally output an “I don’t know” (IDK) on certain input. Given ...
Timely and Non-Disruptive Response of Emergency Vehicles: A Real-Time Approach
Facilitating timely traversal of emergency response vehicles (ERVs), especially through an urban road network remains a challenging task. ERV preemption is a technique commonly used to facilitate prioritized ERV traversal. Unplanned deployment of ERV ...
Crumbs: Utilizing Functional Programming for Hardware Trace Data Analysis
As modern system-on-chip devices are getting more complex, so does their software. Luckily, the observational capabilities of such devices has also increased by providing interfaces for non-intrusive hardware tracing. With these tracing facilities, it ...
Formal schedulability analysis based on multi-core RTOS model
Verification of real-time application schedulability is usually performed using a very abstract representation of the system which poorly supports inter-task dependencies. This paper presents the use of model-checking techniques to check the ...
Contention-Aware GPU Partitioning and Task-to-Partition Allocation for Real-Time Workloads
In order to satisfy timing constraints, modern real-time applications require massively parallel accelerators such as General Purpose Graphic Processing Units (GPGPUs). Generation after generation, the number of computing clusters made available in ...