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=== {{Anchor|Circuit minimization in Boolean algebra}}Boolean expression minimization ===
=== {{Anchor|Circuit minimization in Boolean algebra}}Boolean expression minimization ===
{{Clean up|date=October 2021|reason=We need more consistent, simpler and prose-like summary on every method|section}}
{{Clean up|date=October 2021|reason=We need more consistent, simpler and prose-like summary on every method|section}}
The same methods of boolean expression minimization (simplification) listed below may be applied to the circuit optimization.
The same methods of boolean expression minimization (simplification) listed below may be applied to the [[circuit complexity]] optimization.<ref>https://csrc.nist.gov/Projects/circuit-complexity.</ref>


For the case when the Boolean function is specified by a circuit (that is, we want to find an equivalent circuit of minimum size possible), the unbounded circuit minimization problem was long-conjectured to be [[polynomial hierarchy|<math>\Sigma_2^P</math>-complete]] in [[time complexity]] (the complexity class of decision problems that can be solved on a deterministic Turing machine in polynomial time), a result finally proved in 2008,<ref name="Buchfuhrer_2011"/> but there are effective heuristics such as [[Karnaugh map]]s and the [[Quine–McCluskey algorithm]] that facilitate the process.
For the case when the Boolean function is specified by a circuit (that is, we want to find an equivalent circuit of minimum size possible), the unbounded circuit minimization problem was long-conjectured to be [[polynomial hierarchy|<math>\Sigma_2^P</math>-complete]] in [[time complexity]] (the complexity class of decision problems that can be solved on a deterministic Turing machine in polynomial time), a result finally proved in 2008,<ref name="Buchfuhrer_2011"/> but there are effective heuristics such as [[Karnaugh map]]s and the [[Quine–McCluskey algorithm]] that facilitate the process.

Revision as of 10:00, 30 May 2022

For other uses, see Minimisation.

Logic optimization is a process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. This process is a part of a logic synthesis applied in digital electronics and integrated circuit design.

Generally, the circuit is constrained to a minimum chip area meeting a predefined response delay. The goal of logic optimization of a given circuit is to obtain the smallest logic circuit that evaluates to the same values as the original one.[1] The smaller circuit with the same function is cheaper,[2] takes less space, consumes less power, have shorter latency, and minimizes risks of unexpected cross-talk, hazard of delayed signal processing, and other issues present at the nano-scale level of metallic structures on a integrated circuit.

In terms of Boolean algebra, the optimization of a complex boolean expression is a process of finding a simpler one, which would upon evaluation ultimately produce the same results as the original one.

Motivation

The problem with having a complicated circuit (i.e. one with many elements, such as logic gates) is that each element takes up physical space in its implementation and costs time and money to produce in itself. Circuit minimization may be one form of logic optimization used to reduce the area of complex logic in integrated circuits.

With the advent of logic synthesis, one of the biggest challenges faced by the electronic design automation (EDA) industry was to find the most simple circuit representation of the given design description.[nb 1] While two-level logic optimization had long existed in the form of the Quine–McCluskey algorithm, later followed by the Espresso heuristic logic minimizer, the rapidly improving chip densities, and the wide adoption of Hardware description languages for circuit description, formalized the logic optimization domain as it exists today, including Logic Friday (graphical interface), Minilog, and ESPRESSO-IISOJS (many-valued logic).[3]

Methods

The methods of logic circuit simplifications are equally applicable to the boolean expression minimization.

Classification

Today, logic optimization is divided into various categories:

Based on circuit representation
Two-level logic optimization
Multi-level logic optimization
Based on circuit characteristics
Sequential logic optimization
Combinational logic optimization
Based on type of execution
Graphical optimization methods
Tabular optimization methods
Algebraic optimization methods

Graphical methods

Graphical minimization methods for two-level logic include:

Boolean expression minimization

The same methods of boolean expression minimization (simplification) listed below may be applied to the circuit complexity optimization.[105]

For the case when the Boolean function is specified by a circuit (that is, we want to find an equivalent circuit of minimum size possible), the unbounded circuit minimization problem was long-conjectured to be -complete in time complexity (the complexity class of decision problems that can be solved on a deterministic Turing machine in polynomial time), a result finally proved in 2008,[106] but there are effective heuristics such as Karnaugh maps and the Quine–McCluskey algorithm that facilitate the process.

Boolean function minimizing methods include:

Espresso heuristic logic minimizer

This section is an excerpt from Espresso heuristic logic minimizer § ESPRESSO algorithm.[edit]

A different approach to this issue is followed in the ESPRESSO algorithm, developed by Brayton et al. at the University of California, Berkeley.[120][121] It is a resource and performance efficient algorithm aimed at solving the heuristic hazard-free two-level logic minimization problem.[122]

Rather than expanding a logic function into minterms, the program manipulates "cubes", representing the product terms in the ON-, DC-, and OFF- covers iteratively. Although the minimization result is not guaranteed to be the global minimum, in practice this is very closely approximated, while the solution is always free from redundancy. Compared to the other methods, this one is essentially more efficient, reducing memory usage and computation time by several orders of magnitude. Its name reflects the way of instantly making a cup of fresh coffee. There is hardly any restriction to the number of variables, output functions and product terms of a combinational function block. In general, e.g. tens of variables with tens of output functions are readily dealt with.

The input for ESPRESSO is a function table of the desired functionality; the result is a minimized table, describing either the ON-cover or the OFF-cover of the function, depending on the selected options. By default, the product terms will be shared as much as possible by the several output functions, but the program can be instructed to handle each of the output functions separately. This allows for efficient implementation in two-level logic arrays such as a PLA (Programmable Logic Array) or a PAL (Programmable Array Logic).

The ESPRESSO algorithm proved so successful that it has been incorporated as a standard logic function minimization step into virtually any contemporary logic synthesis tool. For implementing a function in multi-level logic, the minimization result is optimized by factorization and mapped onto the available basic logic cells in the target technology, whether this concerns a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

Two-level versus multi-level representations

While a two-level circuit representation of circuits strictly refers to the flattened view of the circuit in terms of SOPs (sum-of-products) — which is more applicable to a PLA implementation of the design[clarification needed] — a multi-level representation is a more generic view of the circuit in terms of arbitrarily connected SOPs, POSs (product-of-sums), factored form etc. Logic optimization algorithms generally work either on the structural (SOPs, factored form) or functional (Binary decision diagrams, Algebraic Decision Diagrams (ADDs)) representation of the circuit. In sum-of-products (SOP) form, AND gates form the smallest unit and are stitched together using ORs, whereas in product-of-sums (POS) form it is opposite. POS form requires parentheses to group the OR terms together under AND gates, because OR has lower precedence than AND. Both SOP and POS forms translate nicely into circuit logic.

If we have two functions F1 and F2:

The above 2-level representation takes six product terms and 24 transistors in CMOS Rep.

A functionally equivalent representation in multilevel can be:

P = B + C.
F1 = AP + AD.
F2 = A'P + A'E.

While the number of levels here is 3, the total number of product terms and literals reduce [quantify] because of the sharing of the term B + C.

Similarly, we distinguish between sequential and combinational circuits, whose behavior can be described in terms of finite-state machine state tables/diagrams or by Boolean functions and relations respectively. Combinational circuits are defined as the time independent circuits which do not depends upon previous inputs to generate any output are termed as combinational circuits. Examples – Encoder, Decoder, Multiplexer, Demultiplexer.

Sequential circuits are those which are dependent on clock cycles and depends on present as well as past inputs to generate any output. Examples – Flip-flops, Counters.

Example

Original and simplified example circuit

While there are many ways to minimize a circuit, this is an example that minimizes (or simplifies) a Boolean function. The Boolean function carried out by the circuit is directly related to the algebraic expression from which the function is implemented.[123] Consider the circuit used to represent . It is evident that two negations, two conjunctions, and a disjunction are used in this statement. This means that to build the circuit one would need two inverters, two AND gates, and an OR gate.

The circuit can simplified (minimized) by applying laws of Boolean algebra or using intuition. Since the example states that is true when is false and the other way around, one can conclude that this simply means . In terms of logical gates, inequality simply means an XOR gate (exclusive or). Therefore, . Then the two circuits shown below are equivalent, as can be checked using a truth table:

A B (A ∧ B) ∨ (A ∧ B) A ≠ B
F F F F T F T F F F F F
F T F F F T T T T F T T
T F T T T T F F F T T F
T T T F F F F F T T F T

See also

Notes

  1. ^ The netlist size can be used to measure simplicity.

References

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  8. ^ Aiken, Howard Hathaway; Blaauw, Gerrit Anne; Burkhart, William; Burns, Robert J.; Cali, Lloyd; Canepa, Michele; Ciampa, Carmela M.; Coolidge, Jr., Charles A.; Fucarile, Joseph R.; Gadd, Jr., J. Orten; Gucker, Frank F.; Harr, John A.; Hawkins, Robert L.; Hayes, Miles V.; Hofheimer, Richard; Hulme, William F.; Jennings, Betty L.; Johnson, Stanley A.; Kalin, Theodore; Kincaid, Marshall; Lucchini, E. Edward; Minty, William; Moore, Benjamin L.; Remmes, Joseph; Rinn, Robert J.; Roche, John W.; Sanbord, Jacquelin; Semon, Warren L.; Singer, Theodore; Smith, Dexter; Smith, Leonard; Strong, Peter F.; Thomas, Helene V.; Wang, An; Whitehouse, Martha L.; Wilkins, Holly B.; Wilkins, Robert E.; Woo, Way Dong; Little, Elbert P.; McDowell, M. Scudder (1952) [January 1951]. "Chapter V: Minimizing charts". Synthesis of electronic computing and control circuits. The Annals of the Computation Laboratory of Harvard University. Vol. XXVII (second printing, revised ed.). Write-Patterson Air Force Base: Harvard University Press (Cambridge, Massachusetts, USA) / Geoffrey Cumberlege Oxford University Press (London). pp. preface, 50–67. ark:/13960/t4zh1t09d. Retrieved 2017-04-16. p. preface: […] Martha Whitehouse constructed the minimizing charts used so profusely throughout this book, and in addition prepared minimizing charts of seven and eight variables for experimental purposes. […] Hence, the present writer is obliged to record that the general algebraic approach, the switching function, the vacuum-tube operator, and the minimizing chart are his proposals, and that he is responsible for their inclusion herein. […] (2+x+278+2 pages) (NB. Work commenced in April 1948.)
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  13. ^ Ashenhurst, Robert "Bob" Lovett [at Wikidata] (January 1953) [1952-09-01, 1953-01-01]. "The decomposition of switching functions". Bell Laboratories' Report (report) (BL-1). Harvard Computation Laboratory, Harvard University, Cambridge, Massachusetts, USA: Bell Laboratories: II-1–II-37. PB122812. (37 of 98 pages) (NB. This article was reprinted in the appendix of Curtis (1962), pp. 571–602.); another article of the same title was published as: Ashenhurst, Robert "Bob" Lovett [at Wikidata] (December 1956) [1956-05-01, 1956-12-01]. Aiken, Howard Hathaway (ed.). "The decomposition of switching functions". Bell Laboratories' Report / Theory of Switching (report) (BL-16). Harvard Computation Laboratory, Harvard University, Cambridge, Massachusetts, USA: Bell Laboratories: III-1–III-72. PB147348. (72 of 193 pages); an updated article was later published under the same title as: Ashenhurst, Robert "Bob" Lovett [at Wikidata] (1957-04-02). "The Decomposition of Switching Functions" (PDF). Proceedings of the International Symposium on the Theory of Switching, Part I. The Annals of the Computation Laboratory of Harvard University. XXIX. Harvard University, Cambridge, Massachusetts, USA: Harvard University Press (published 1959): 74–116. Archived (PDF) from the original on 2021-03-28. Retrieved 2021-03-29. (43 pages)
  14. ^ Singer, Theodore "Ted" (July 1953) [1953-04-01, 1953-07-01]. "The Decomposition Chart as a Theoretical Aid". Bell Laboratories' Report (report) (BL-4). Harvard Computation Laboratory, Harvard University, Cambridge, Massachusetts, USA: Bell Laboratories: III-1–III-28. PB122815. (28 of 149 pages) (NB. This article was reprinted in the appendix of Curtis (1962), pp. 602–620.)
  15. ^ Ashenhurst, Robert "Bob" Lovett [at Wikidata] (July 1953) [1953-04-01, 1953-07-01]. "Non-disjoint Decomposition". Bell Laboratories' Report (report) (BL-4). Harvard Computation Laboratory, Harvard University, Cambridge, Massachusetts, USA: Bell Laboratories: IV-1–IV-12. PB122815. (12 of 149 pages) (NB. This article was reprinted in the appendix of Curtis (1962), pp. 620–630.)
  16. ^ Veitch, Edward Westbrook (1952-05-03) [1952-05-02]. "A Chart Method for Simplifying Truth Functions". Transactions of the 1952 ACM Annual Meeting. ACM Annual Conference/Annual Meeting: Proceedings of the 1952 ACM Annual Meeting (Pittsburgh, Pennsylvania, USA). New York, USA: Association for Computing Machinery (ACM): 127–133. doi:10.1145/609784.609801.
  17. ^ Svoboda, Antonín (1955-11-27) [1955-11-22]. Graphisch-mechanische Hilfsmittel für die Synthese von Relaisschaltungen [Graphical-mechanical aids for the synthesis of relay circuits] (Report). Dresden, Germany: Internationales Mathematiker-Kolloquium über aktuelle Probleme der Rechentechnik. pp. 43–50. (NB. According to Constantinescu the contents might be identical to a journal article in 1956.)
  18. ^ Svoboda, Antonín (1956). Graficko-mechanické pomůcky užívané při analyse a synthese kontaktových obvodů [Utilization of graphical-mechanical aids for the analysis and synthesis of contact circuits]. Stroje na zpracování informací [Symposium on information processing machines] (in Czech). Vol. IV. Prague: Czechoslovak Academy of Sciences, Research Institute of Mathematical Machines. pp. 9–22.{{cite conference}}: CS1 maint: date and year (link)
  19. ^ Svoboda, Antonín (1956). (unknown) [Graphical-Mechanical Aids for the Synthesis of Relay Circuits] (in Czech). Vol. 4. Braunschweig, Germany: Friedrich Vieweg & Sohn. pp. 213–218. ECIP55 213. {{cite book}}: |journal= ignored (help); Cite uses generic title (help)CS1 maint: date and year (link) (NB. According to Constantinescu the contents might be identical to a congress report in 1955.)
  20. ^ Svoboda, Antonín (1959) [1957-03-29]. "Some Applications of Contact Grids". Proceedings of an International Symposium on the Theory of Switching, 2–5 April 1957, Part I. The Annals of the Computation Laboratory of Harvard University. Vol. XXIX. Harvard University, Cambridge, Massachusetts, USA: Harvard University Press. pp. 293–305. (305 pages)
  21. ^ Svoboda, Antonín (1958). (unknown) [Graphical aids to minimization in switching circuits]. Stroje na zpracování informací [Symposium on information processing machines] (in Czech). Vol. VI. Prague: Czechoslovak Academy of Sciences, Research Institute of Mathematical Machines. pp. 35–53. {{cite conference}}: Cite uses generic title (help)
  22. ^ McNaughton, Robert Forbes (March 1958). "Antonin Svoboda. Graphico-mechanical aids for the synthesis of relay circuits. Aktuelle Probleme der Rechentechnik, Deutscher Verlag der Wissenschaften, Berlin 1957, pp. 43–50". Journal of Symbolic Logic (Review). 23 (1): 60–61. doi:10.2307/2964502. Retrieved 2020-05-14. p. 60: The two graphico-mechanical aids are contact bones and contact grids. Contact bones are an aid in analyzing (i.e., finding a logical formula for) contact networks. The logical theory of contact network analysis has been generally understood for a long time, but there are practical difficulties, especially in the analysis of bridge networks (i.e., networks which are not of the series-parallel type). Contact grids are an aid in obtaining a normal formula for functions given in truth-table form. They are helpful in obtaining what are called (by others) prime implicants. […] (NB. This review is about Svoboda's congress report.)
  23. ^ Constantinescu, Paul (1959-12-22). "Svoboda, Antonin. Graphical-mechanical aids for the synthesis of relay circuits. Elektronische Rechenmaschinen und Informationsverarbeitung, 213–218 (1956). — Ber. Internat. Math.-Kolloquium Dresden, 22. bis 27. Nov. 1955, 42–50 (1957)". Zentralblatt für Mathematik (Review). 82 (1): 126. Zbl 0082.12602. Archived from the original on 2020-05-14. Retrieved 2020-05-14. p. 126: The author utilizes interesting mechanical aids in solving problems concerning contact networks. The basis for the creation of these aids is the fact that each independent variable may be expressed by a Boolean sum of variables which define the state of the network. Employing "contact bones" and "contact grids" the author achieves the analysis and synthesis of a contact network and the transformation of the Boolean functions given in tabular form in algebraic form. (NB. This review is about Svoboda's congress report and journal article.)
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  32. ^ Roginskij [Рогинский], Vadim Nikolaevich [Вадим Николаевич] (1957). "(unknown)" [Graphical method of synthesizing contact networks]. Èlektrosvâzʹ (in Russian). XI (11): 82–88. ISSN 0013-5771. {{cite journal}}: Cite uses generic title (help)
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  35. ^ Händler, Wolfgang (1958-12-19). Ein Minimisierungsverfahren zur Synthese von Schaltkreisen (Minimisierungsgraphen) (Dissertation) (in German). Potsdam, Germany: Technische Hochschule Darmstadt. D 17. (73 pages+app.) [8]
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  37. ^ Berger, Erich R.; Händler, Wolfgang (1967) [1962]. Steinbuch, Karl W.; Wagner, Siegfried W. (eds.). Taschenbuch der Nachrichtenverarbeitung (in German) (2 ed.). Berlin, Germany: Springer-Verlag OHG. pp. 64, 1034–1035, 1036, 1038. LCCN 67-21079. Title No. 1036. p. 64: […] Übersichtlich ist die Darstellung nach Händler, die sämtliche Punkte, numeriert nach dem Gray-Code […], auf dem Umfeld eines Kreises anordnet. Sie erfordert allerdings sehr viel Platz. […] [Händler's illustration, where all points, numbered according to the Gray code, are arranged on the circumference of a circle, is easily comprehensible. It needs, however, a lot of space.]
  38. ^ Dokter, Folkert; Steinhauer, Jürgen (1973-06-18). "3.7.1. Händler's diagram". Digital Electronics. Philips Technical Library (PTL) / Macmillan Education (Reprint of 1st English ed.). Eindhoven, Netherlands: The Macmillan Press Ltd. / N. V. Philips' Gloeilampenfabrieken. pp. 108–111. doi:10.1007/978-1-349-01417-0. ISBN 978-1-349-01419-4. SBN 333-13360-9. Retrieved 2020-05-11. (270 pages) (NB. This is based on a translation of volume I of the two-volume German edition.)
  39. ^ Dokter, Folkert; Steinhauer, Jürgen (1975) [1969]. "3.7.1. Kreisgraphen nach Händler". Digitale Elektronik in der Meßtechnik und Datenverarbeitung: Theoretische Grundlagen und Schaltungstechnik. Philips Fachbücher (in German). Vol. I (improved and extended 5th ed.). Hamburg, Germany: Deutsche Philips GmbH. pp. 115, 124, 129, 130–134 [130–134]. ISBN 3-87145-272-6. (xii+327+3 pages) (NB. The German edition of volume I was published in 1969, 1971, two editions in 1972, and 1975. Volume II was published in 1970, 1972, 1973, and 1975.)
  40. ^ Klar, Rainer (1970-02-01). "2.4.2 Graphische Minimisierungsverfahren" [2.4.2 Graphical minimisation methods]. Digitale Rechenautomaten – Eine Einführung [Digital Computers – An Introduction]. Sammlung Göschen (in German). Vol. 1241/1241a (1 ed.). Berlin, Germany: Walter de Gruyter & Co. / G. J. Göschen'sche Verlagsbuchhandlung [de]. pp. 70–73. ISBN 3-11-083160-0. ISBN 978-3-11-083160-3. Archiv-Nr. 7990709. Archived from the original on 2020-04-13. Retrieved 2020-04-13. pp. 70–72: […] Der Kreisgraph nach Händler ordnet den einzelnen Mintermen Knoten eines Graphen zu. Die Nachbarschaft von Mintermen wird durch Kanten dargestellt, die die entsprechenden Knoten miteinander verbinden. Bei dem "Kreisgraph" liegen sämtliche Knoten auf einem Kreis. Um symmetrische Kanten zu bekommen, wird die Reihenfolge der Knoten (bzw. Minterme) durch den reflektierten Gray-Code festgelegt, der sich durch fortlaufende Spiegelung und Ergänzung konstruieren läßt. Die negierten Variablen werden dabei durch Nullen, die nichtnegierten durch Einsen dargestellt. Man beginnt mit einer Variablen, die negiert (0) oder nichtnegiert (1) auftritt. Die 0 und 1 werden gespiegelt. Durch Anfügen einer Null vor 0 und 1 und einer Eins vor die Spiegelbilder werden Terme mit 2 Variablen gebildet. Die Spiegelung und das Anfügen von Nullen und Einsen wird wiederholt, bis die gewünschte Zahl von n Variablen und 2n Termen erreicht ist. […] Das Minimisierungsverfahren mit dem Kreisgraphen verläuft in folgenden Schritten: I. Aufstellung der DKF [disjunktive kanonische Form]. II. Alle Knoten, die auftretende Minterme repräsentieren, werden gekennzeichnet. III. Alle Kanten, die markierte Knoten verbinden, werden gekennzeichnet. Der so entstandene Untergraph markiert sämtliche Primimplikanten. Er setzt sich zusammen aus folgenden Unterstrukturen: isolierten Knoten (Primimplikant der Länge n), 21 verbundenen Knoten (Primimplikant der Länge n−1), 22 verbundenen Knoten (Primimplikant der Länge n−2), 23 verbundenen Knoten (Primimplikant der Länge n−3) usw. Das Auffinden der wesentlichen Primimplikanten und der Restüberdeckung bleibt wie beim Karnaugh-Veitch-Diagramm der Geschicklichkeit überlassen. […] (205 pages) (NB. A 2019 reprint of the first edition is available under ISBN 3-11002793-3, 978-3-11002793-8. A reworked and expanded 4th edition exists as well.)
  41. ^ Klar, Rainer (1989) [1988-10-01]. "2.4.2 Graphische Minimisierungsverfahren" [2.4.2 Graphical minimisation methods]. Digitale Rechenautomaten – Eine Einführung in die Struktur von Computerhardware [Digital Computers – An Introduction into the structure of computer hardware]. Sammlung Göschen (in German). Vol. 2050 (4th reworked ed.). Berlin, Germany: Walter de Gruyter & Co. pp. 94–97. ISBN 3-11011700-2. ISBN 978-3-11011700-4. (320 pages)
  42. ^ Hotz, Günter (1974). Schaltkreistheorie [Switching circuit theory]. DeGruyter Lehrbuch (in German) (1 ed.). Walter de Gruyter & Co. p. 117. ISBN 3-11-00-2050-5. Archived from the original on 2020-04-13. Retrieved 2020-04-13. p. 117: […] Der Kreisgraph von Händler ist für das Auffinden von Primimplikanten gut brauchbar. Er hat den Nachteil, daß er schwierig zu zeichnen ist. Diesen Nachteil kann man allerdings durch die Verwendung von Schablonen verringern. […] [The circle graph by Händler is well suited to find prime implicants. A disadvantage is that it is difficult to draw. This can be remedied using stencils.]
  43. ^ "Informatik Sammlung Erlangen (ISER)" (in German). Erlangen, Germany: Friedrich-Alexander Universität. 2012-03-13. Archived from the original on 2017-05-16. Retrieved 2017-04-12. (NB. Shows a picture of a Kreisgraph by Händler.)
  44. ^ "Informatik Sammlung Erlangen (ISER) - Impressum" (in German). Erlangen, Germany: Friedrich-Alexander Universität. 2012-03-13. Archived from the original on 2012-02-26. Retrieved 2017-04-15. (NB. Shows a picture of a Kreisgraph by Händler.)
  45. ^ Zemanek, Heinrich "Heinz" Josef (2013) [1990]. "Geschichte der Schaltalgebra" [History of circuit switching algebra]. In Broy, Manfred (ed.). Informatik und Mathematik [Computer Sciences and Mathematics] (in German). Springer-Verlag. pp. 43–72. doi:10.1007/978-3-642-76677-0_3. ISBN 9783642766770. ISBN 3642766773. p. 58: Einen Weg besonderer Art, der damals zu wenig beachtet wurde, wies W. Händler in seiner Dissertation […] mit einem Kreisdiagramm. […] (NB. Collection of papers at a colloquium held at the Bayerische Akademie der Wissenschaften, 1989-06-12/14, in honor of Friedrich L. Bauer.)
  46. ^ Bauer, Friedrich Ludwig; Wirsing, Martin (March 1991). Elementare Aussagenlogik (in German). Berlin / Heidelberg: Springer-Verlag. pp. 54–56, 71, 112–113, 138–139. ISBN 3-540-52974-8. ISBN 978-3-540-52974-3. p. 54: […] handelt es sich um ein Händler-Diagramm […], mit den Würfelecken als Ecken eines 2m-gons. […] Abb. […] zeigt auch Gegenstücke für andere Dimensionen. Durch waagerechte Linien sind dabei Tupel verbunden, die sich nur in der ersten Komponente unterscheiden; durch senkrechte Linien solche, die sich nur in der zweiten Komponente unterscheiden; durch 45°-Linien und 135°-Linien solche, die sich nur in der dritten Komponente unterscheiden usw. Als Nachteil der Händler-Diagramme wird angeführt, daß sie viel Platz beanspruchen. […]
  47. ^ Peticolas, Alfred B.; Mahoney, Matthew V. (1963-12-20). Computer circuits and computer systems (Laboratory manual). New York, USA: RCA Institutes, Inc. C-15. A674036. (NB. This work formed the basis for the 1964 course manual.)
  48. ^ Peticolas, Alfred B.; Mahoney, Matthew V. (1964-08-10). Logical Design for Digital Systems. New York, USA: RCA Institutes, Inc. A715535. N65-25354. [9][10] (191+1 pages) (NB. This course manual is based on the 1963 laboratory manual.)
  49. ^ Peticolas, Alfred B.; Mahoney, Matthew V.; Laguzzi, Mario C., eds. (1967-05-08) [1966]. Logic Design (lecture notes) (4 ed.). New York, USA: RCA Institutes, Inc. A917290. (185 pages) (NB. This fourth edition of a course student binder, based on the earlier manual, is mentioned in a 1968 RCA flyer.)
  50. ^ School of Custom Educational Program (1966-07-22). Logic Design (flyer). New York, USA: RCA Institutes, Inc. CE-105-R56. ark:/13960/t56f22q9v. Retrieved 2021-02-20. […] Staff […] Bradford Daggett, Director […] Matthew V. Mahoney, Admin., Development […] Alfred B. Peticolas, Dean […] Mario C. Laguzzi, Member of Technical Staff […] Edward K. Marrie, Member of Technical Staff […] Abraham Schwartz, Member of Technical Staff […] [11]
  51. ^ "Logic Design: Development of the Mahoney Map". Written at Syracuse, New York, USA. A Syllabus on the Content of Logic Design: A Five-day Educational Seminar For Engineers Presented by RCA Institutes (flyer). New York, USA: RCA Institutes, Inc. 1968-11-25. ark:/13960/t8kd8cx8z. Retrieved 2021-02-20. […] The Planning Board […] This seminar has been developed through extensive field research by the Institute for Professional Development in consultation with RCA Institutes' Board of Technical Advisers, representing various technical research and educational activities of RCA and its subsidiaries. […] B. I. Daggett (Director), J. H. Sneddon (Manager, Administration), D. B. Kenney (Industrial Sales), B. V. Ferguson (Direct Marketing), M. V. Mahoney (Research & Development), A. B. Peticolas (Administrator), J. B. Wetterau (Group Leader), E. Fleisher (Staff Member), M. C. Laguzzi (Staff Member), R. D. Lindskog (Staff Member), C. L. Pearce (Staff Member), P. Pennisi (Staff Member), C. H. Saville (Staff Member), R. E. Weiss (Staff Member) […] Table of Contents […] The Matrix Approach to Logic Designation Number Notation […] Designation Numbers of Boolean Elements and Functions, Logical Operations with Designation Numbers […] The Logic Map […] Development of the Mahoney Map […] [12] (NB. This 1968 flyer mentions Mahoney as RCA R&D member. A 184 pages lecture notes binder was available to course members.)
  52. ^ "Logic Design: Development of the Mahoney Map". Written at Montreal, Quebec, Canada. RCA - A Course in Logic Design - A unique learning experience for those who solve digital circuit design problems, or who evaluate Logic Design effectiveness - A seminar prepared by the Institute for Professional Development of RCA Institutes (flyer). Clark, New Jersey, USA: RCA Institutes, Inc. 1970-08-24. p. 2.5. ark:/13960/t7jq7zk56. Retrieved 2021-02-16. p. 2.5: […] RCA courses for Professional Development, since our programs were first formed in 1964. […] Logic Design […] The reduction technique to be explored below and used henceforth in our logic design work is a variation on the Veitch diagram. This modification, introduced by M. V. Mahoney, is designed to work directly from designation numbers; the designer need never see a Boolean expression other than the final, simplified form. With this particular map, the position of each minterm is invariant, regardless of the number of variables, so that the map pattern is easily memorized. […] Definitions and Basic Concepts […] Let f = any function […] #f = the designation number of f (read "designation f") […] n = number of variables (f is a function of n variables) […] p = number of positions in #f […] p = number of square subsets in universe […] i = position identification […] mi = the minterm occupying position i […] We will first assume that n = 0. As with the original Venn diagram, the universe will be a rectangle. With n = 0, we cannot subdivide this universal set. There is no need to, however, for if n = 0, p = 20 = 1. In other words, there is only one position in #f, the zero position, and only one possible minterm, m0. The rectangular universe will represent m0 and will be marked with the minterm subscript: […] n = 0 [o] No. of subsets (squares) = no. of minterm positions = p = 2n = 20 = 1 […] Although there are no variables, there are still 2p = 2 functions possible. These functions must be the two constants, 1 and 0. […] If f = 0, then #f = 0; i.e. m0 is empty. This is indicated by leaving the diagram unmarked: [o] #f = 0; f = 0; p = 2n = 1 […] If f = 1, then #f = 1; i.e. the m0 position is occupied. This is indicated with a diagonal mark: [/o/] #f = 1; f = 1; f = m0 […] The above map would, of course, never be needed in a practical problem. Here it is used only as an introduction, for the orderly evolution of the general n-variable map. […] Map Development […] Visualize the map as a large sheet marked with a checkerboard pattern of squares. Now fold the lower half upwards so it is hidden behind the top. Fold the right hand half behind the left. Repeat the above procedures alternately, until only the single upper left square remains visible. This square is the set representing minterm zero, the square used as our starting point. […] {{cite book}}: |work= ignored (help) [13] (NB. This 1970 flyer mentions that the course was established in 1964.)
  53. ^ Fezer, Harold (December 1970 – January 1971). "The evolution and development of RCA Institutes" (PDF). RCA Engineer. 16 (4). New Jersey, USA: RCA Corporate Engineering Services / RCA Corporation: 64–69 [67]. Archived (PDF) from the original on 2021-02-19. Retrieved 2021-02-19. p. 67: Logic design (5 days) - provides the numerical and matrix tools required to select the most straightforward, practical approach to digital circuit design. The Mahoney Map and designation numbers are thoroughly covered. [14]
  54. ^ Moser, Jr., Carl Woodrow (1973-07-19) [January 1973]. Written at Western Electric, Winston-Salem, North Carolina, USA. "Checking wired-AND gates in just one test setup". Engineer's notebook. Electronics - The International Magazine of Electronics Technology. Vol. 46, no. 15. New York, USA: McGraw-Hill, Inc. p. 127. ISSN 0013-5070. Archived from the original on 2021-02-16. Retrieved 2021-02-16. p. 127: […] One of the most difficult types of circuits to test effectively is an array of wired-AND logic gates. But a standard design aid, the Mahoney map, can be used to determine the best waveform setup for completely testing such an array. The Mahoney map is identical to the Karnaugh map, with the exception of the minterm digits. […] [15][16] (1 page)
  55. ^ van Holten, Cornelis "Cornelius" (August 1974). Written at Delft Technical University, Delft, Netherlands. "Double multiplexer logic capability - by using one of the input variables to drive some data lines. A modified Karnaugh map helps you choose the right ones". Electronic Design - For Engineers and Engineering Managers. Vol. 22, no. 17. Rochelle Park, New Jersey, USA: Hayden Publishing Company, Inc. pp. 86–89 [87, 89]. ISSN 0013-4872. Retrieved 2021-02-20. (4 pages)
  56. ^ Krehbiel, Paul (1996-12-05). Bonal, David (ed.). (Private communication). (NB. Cited in Bonal.[17])
  57. ^ Mann, Kenneth (2005-12-18) [2005-11-19]. "Karnaugh Maps Tutorial". PhysicsForums. Archived from the original on 2021-02-16. Retrieved 2021-02-16. […] about a decade after Karnaugh's paper, an individual named Matthew Mahoney observed a symmetrical reflecting approach behind the process of map construction which showed that maps could be extended in design beyond four variables, and from that approach he came up with a slightly different design which, was termed the 'Mahoney Map'. […] In the early 1960s, Matthew Mahoney more precisely defined the basic mechanism through which the logic-map operates. Using this principle (which we have already laid out) he defined and laid out what came to be called the "Mahoney-Map". Essentially, the Mahoney Map is a variation of the Karnaugh Map, and the principles will apply equally in both cases. […] [18][19]
  58. ^ Goth, Andrew "Andy" Michael (2012-11-27) [2009-01-28]. "Mahoney Map - An alternative to Karnaugh Maps". Midlothian, Texas, USA. Archived from the original on 2021-02-16. Retrieved 2021-02-16.
  59. ^ Bonal, David (2013-10-19). "Karnaugh and Mahoney: Map Methods for Minimizing Boolean Expressions". Section 3. Mahoney Maps: Implementing the Sign of Zoro. Archived from the original on 2021-02-16. Retrieved 2021-02-16.
  60. ^ Kortum, Herbert Franz [in German] (1965). "Minimierung von Kontaktschaltungen durch Kombination von Kürzungsverfahren und Graphenmethoden" [Minimization of contact circuits by combination of reduction procedures and graphical methods]. messen-steuern-regeln (msr) (in German). 8 (12). Berlin / Leipzig, Germany: VEB Verlag Technik [de]: 421–425. ISSN 0026-0347. OCLC 310970250. CODEN MSRGAN, MSRGA, MMSRD. DNB-IDN 01269357X. ZDB-ID 512087-1. Retrieved 2020-11-04. (5 pages)
  61. ^ Kortum, Herbert Franz [in German] (1966). "Konstruktion und Minimierung von Halbleiterschaltnetzwerken mittels Graphentransformation". messen-steuern-regeln (msr) (in German). 9 (1). Berlin / Leipzig, Germany: VEB Verlag Technik [de]: 9–12. ISSN 0026-0347. OCLC 310970250. CODEN MSRGAN, MSRGA, MMSRD. DNB-IDN 01269357X. ZDB-ID 512087-1. Retrieved 2018-06-17.{{cite journal}}: CS1 maint: url-status (link)
  62. ^ Kortum, Herbert Franz [in German] (1966). "Weitere Bemerkungen zur Minimierung von Schaltnetzwerken mittels Graphenmethoden". messen-steuern-regeln (msr) (in German). 9 (3). Berlin / Leipzig, Germany: VEB Verlag Technik [de]: 96–102. ISSN 0026-0347. OCLC 310970250. CODEN MSRGAN, MSRGA, MMSRD. DNB-IDN 01269357X. ZDB-ID 512087-1. Retrieved 2018-06-17.{{cite journal}}: CS1 maint: url-status (link)
  63. ^ Kortum, Herbert Franz [in German] (1965). "Weitere Bemerkungen zur Behandlung von Schaltnetzwerken mittels Graphen" [Further remarks on treatment of switching networks by means of graphs]. Regelungstechnik (Conference paper). 10. Internationales Wissenschaftliches Kolloquium. [10th international scientific colloquium] (in German). 10 (5). Technische Hochschule Ilmenau: 33–39. Retrieved 2020-11-04 (7 pages); Kortum, Herbert Franz [in German] (1966). "Weitere Bemerkungen zur Behandlung von Schaltnetzwerken mittels Graphen. Konstruktion von vermaschten Netzwerken (Brückenschaltungen)" [Further remarks on treatment of switching networks by means of graphs]. messen-steuern-regeln (msr) (in German). 9 (5). Berlin / Leipzig, Germany: VEB Verlag Technik [de]: 151–157. ISSN 0026-0347. OCLC 310970250. CODEN MSRGAN, MSRGA, MMSRD. DNB-IDN 01269357X. ZDB-ID 512087-1.
  64. ^ Kortum, Herbert Franz [in German] (1967). "Über zweckmäßige Anpassung der Graphenstruktur diskreter Systeme an vorgegebene Aufgabenstellungen". messen-steuern-regeln (msr) (in German). 10 (6). Berlin / Leipzig, Germany: VEB Verlag Technik [de]: 208–211. ISSN 0026-0347. OCLC 310970250. CODEN MSRGAN, MSRGA, MMSRD. DNB-IDN 01269357X. ZDB-ID 512087-1.
  65. ^ Kortum, Herbert Franz [in German] (1966) [1965]. "Zur Minimierung von Schaltsystemen" [Minimization of switching circuits]. Wissenschaftliche Zeitschrift der TU Ilmenau (in German). 12 (2). Jena, Germany: Technische Hochschule für Elektrotechnik Ilmenau / Forschungsstelle für Meßtechnik und Automatisierung der Deutschen Akademie der Wissenschaften: 181–186. Retrieved 2020-11-04. (6 pages)
  66. ^ Tafel, Hans Jörg (1971). "4.3.5. Graphenmethode zur Vereinfachung von Schaltfunktionen". Written at RWTH, Aachen, Germany. Einführung in die digitale Datenverarbeitung [Introduction to digital information processing] (in German). Munich, Germany: Carl Hanser Verlag. pp. 98–105, 107–113. ISBN 3-446-10569-7.
  67. ^ Axmann, Hans-Peter (2019) [1979-06-13]. Einführung in die technische Informatik: Funktionsweise digitaler Bausteine und deren Verwendung in Datenerfassungssystemen (in German) (reprint of 1st ed.). Springer-Verlag Wien GmbH. p. 37. doi:10.1007/978-3-7091-4478-7. ISBN 978-3-211-81546-5. Retrieved 2020-04-15. p. 37: […] Die Graphenmethode zur Vereinfachung von Schaltfunktionen zeichnet sich durch besondere Anschaulichkeit und Einfachheit aus. Sie ist dann besonders vorteilhaft, wenn die Schaltfunktion unter Verwendung bestimmter Verknüpfungsglieder mit minimalem Aufwand an Bauelementen und Verbindungsleitungen zu realisieren ist. Sie ist anderen Methoden, besonders bei der Netzwerksynthese von Brückenschaltungen wie auch bei der Optimierung von Kontaktschaltungen mit Sperrdioden, überlegen. Die erfolgreiche Anwendung der Graphenmethode setzt voraus, daß die vorgegebene Funktion bereits in einer weitgehend vereinfachten Form vorliegt, da mit dieser Methode Redundanzen nur noch sehr schwer zu eliminieren sind. […] (290 pages)
  68. ^ Winkler, Jürgen F. H. (2013-04-07) [2008-10-25]. "Die Oprema – der Relaisrechner des Zeisswerks Jena" (PDF) (Lecture notes) (in German). Friedrich Schiller University, Jena, Germany. pp. 1–27. Archived from the original (PDF) on 2017-08-30. (27 pages)
  69. ^ Winkler, Jürgen F. H. (2019-08-26) [2014-10-25]. "Oprema – The Relay Computer of Carl Zeiss Jena" (PDF). 1. Friedrich Schiller University, Jena, Germany. pp. 1–33. arXiv:1908.09549. Archived (PDF) from the original on 2020-09-29. Retrieved 2020-11-04. (33 pages)
  70. ^ a b Burgoon, J. Robert "Rob" (1972-12-21). Written at Hewlett-Packard, Santa Clara Division, Santa Clara, California, USA. "Improve your Karnaugh mapping skills. Use of variables allows you to simplify maps and design circuits for latching or sequential-signal gating" (PDF). Electronic Design - For Engineers and Engineering Managers. Vol. 20, no. 26. Rochelle Park, New Jersey, USA: Hayden Publishing Company, Inc. pp. 54–56. ISSN 0013-4872. Archived (PDF) from the original on 2021-02-14. Retrieved 2021-02-14. (3 pages) (NB. A slight extension of this method by Larry L. Dornhoff is discussed in Muroga.)
  71. ^ a b Vingron, Shimon Peter (2004) [2003-11-05]. "Chapter 20. Reduced Karnaugh Maps". Switching Theory: Insight Through Predicate Logic (1 ed.). Berlin, Heidelberg, New York: Springer-Verlag. pp. 207–217. doi:10.1007/978-3-662-10174-2. ISBN 3-540-40343-4.
  72. ^ a b Vingron, Shimon Peter (2012). "5.5 Karnaugh Trees and Map-Entered Variables". Written at Hinterbrühl, Austria. Logic Circuit Design: Selected Methods (1 ed.). Berlin & Heidelberg, Germany: Springer-Verlag. pp. 63–66. doi:10.1007/978-3-642-27657-6. ISBN 978-3-642-43256-9. (xiv+258 pages)
  73. ^ Schultz, G. W. (March 1969). Written at Central Data Systems, Inc., Sunnyvale, California, USA. "An Algorithm for the Synthesis of Complex Sequential Networks". Computer Design. Vol. 8, no. 3. Concord, Massachusetts, USA: Computer Design Publishing Corporation. pp. 49–55. ISSN 0010-4566. OCLC 828863003. CODEN CMPDA. Retrieved 2021-02-22. (7 pages) (NB. This article caused a number of letters to the editor in subsequent issues of the magazine.)
  74. ^ a b Schultz, G. W. (1969). Written at Central Data Systems, Inc., Sunnyvale, California, USA. "To the Editor". Letters to the editor. Computer Design. Vol. 8, no. 5–12?. Concord, Massachusetts, USA: Computer Design Publishing Corporation. p. 10. ISSN 0010-4566. OCLC 828863003. CODEN CMPDA. p. 10: […] In your April issue you published a letter by R. L. Dineley describing a simple method for treating product-of-sums logical expressions. […] An even simpler method is taught by D. A. Huffman. This method is based on recognizing that the Boolean expression will be zero when any of the factors in the product-of-sums form is zero. Plotting zeroes of factors on a Veitch diagram or Karnaugh map is as easy as locating ones for a sum-of-products expression. […] To illustrate, using Dineley's example (A+BC)(A+C): […] The zeroes resulting from A+BC will be located wherever both A and BC are zero. Therefore we locate on the map the expression A*BC (which is equal to A*B + A*C). Similarly the zeroes of A+C are located and plotted at A*C. With all zeroes located, the rest of the map can be filled with ones. One can be a little more formal and work out algebraically the logical complement of the expression under consideration and then plot zeroes for that resulting expression. In a simple product-of-sums representation, however, the complementary terms can be written by inspection; or the zeroes can be plotted by inspection without writing the complete expression […] "Classical Reduction Involving Infrequently Used Variables" October 11, 1968. University of Santa Clara […] Mr. Osborne's work draws close similarity to that I presented in this article and thus, would certainly be of interest to those readers seeking further information. I understand he has done work to apply the technique of infrequent variables to the design of sequential networks constructed from Read Only Memory. Since he has not yet published anything on this area, if readers would like additional information, they can write Mr. Osborne at: […] Thomas E. Osborne […] Building 1U […] 1501 Page Mill Road […] Palo Alto, California […] Thank you for the opportunity to publish with you. […] G. W. Schultz […] Central Data Systems, Inc. […] Sunnyvale, Calif. (1 page) (NB. Osborne's method was later published by Clare.[B])
  75. ^ Langdon, Jr., Glen G. (1974). "Chapter 4. Interrelationships, D. Logic Design and Switching Theory, 3. The Flow Table as a Point of Departure for Design". Written at IBM Corporation, San Jose, California, USA. In Ashenhurst, Robert "Bob" Lovett [at Wikidata] (ed.). Logic Design - A Review of Theory and Practice. ACM Monograph Series (1 ed.). New York, USA: Academic Press, Inc. - A Subsidiary of Harcourt Brace Jovanovich, Publishers. p. 149. ISBN 0-12-436550-7. ISSN 0572-4252. LCCN 73-18988. ISBN 978-0-12-436550-6. Archived from the original on 2021-04-17. Retrieved 2021-04-17. p. 149: […] An important contribution to the adaptation of theory to practice was made by Schultz [20]; he draws upon the designer's basic understanding of the problem and requires him to identify the "infrequent variables." Loosely defined, these variables do not relate to all internal states, i.e., they are not needed to define every state. In essence, the infrequent variables are relevant to only a few (perhaps one or two) states or state transitions. Schultz suggests that the designer first translate the verbal problem to a state transition graph that is reduced. The internal states are encoded and then information regarding infrequent variables is added to the appropriate state transitions. A "first approximation" to flip-flop input equations is made, based only upon the frequent variables. Schultz demonstrates how these equations can subsequently be modified to incorporate transitions controlled by the infrequent variables. In Schultz's examples the infrequent variables are all input signals, but this idea also applies to internal state variable signals that may be considered "infrequent." In this case, for example, an infrequent internal state variable flip-flop might be set by a particular circumstance and reset sometime later. The output of the flip-flop may now be treated as an infrequent input variable. […] (ix+1+179+3 pages)
  76. ^ Clare, Christopher "Chris" R. (February 1971) [November 1970]. Logic Design of Algorithmic State Machines. Hewlett-Packard Laboratories, USA: Hewlett-Packard. CHM Catalog Number 102650285. (110 pages) [20] (NB. Several internal revisions existed in 1970 and 1971. This was later published by McGraw-Hill.[A] Thomas E. Osborne's simplification method was already mentioned by G. W. Schultz in 1969.)
  77. ^ Clare, Christopher "Chris" R. (1973) [November 1972]. "Reducing the Required Map Size with Map-Entered Variables". Designing Logic Systems Using State Machines. Osborne, Thomas "Tom" E. (initial contributions) (1 ed.). Electronics Research Laboratory, Hewlett-Packard Laboratories: McGraw-Hill, Inc. pp. 41–42. ISBN 0-07011120-0. S2CID 60509061. SBN 07-011120-0. ISBN 978-0-07011120-2. ark:/13960/t9383kw8n. 79876543. Retrieved 2021-02-14. (2 pages of vii+114+3 pages) [21] (NB. This book is based on a 1970 Hewlett-Packard in-house document.[B] A slight extension of this method by Larry L. Dornhoff is discussed in Muroga.)
  78. ^ a b Muroga, Saburo (1979). Logic Design and Switching Theory (1 ed.). New York, USA: John Wiley and Sons, Inc. pp. 161–163. ISBN 0-47104418-0. ISBN 978-0-47104418-5. (3 pages of 617 pages); Muroga, Saburo (January 1990) [1979]. Logic Design and Switching Theory (updated reprint ed.). Malabar, Florida, USA: Robert E. Krieger Publishing Company, Inc. pp. 161–163. ISBN 0-89464-463-7. LCCN 90-32076. (617+5-6+32 pages) (NB. Original chapters 6.3–6.6 (pages 281–320) were replaced by new chapters 6.3–6.5 (inserted pages 1–32); also in 1997 under ISBN 1-57524036-X, 978-1-57524036-7. The method described here is a slight extension by Larry L. Dornhoff of the method discussed in Burgoon and Clare. A further extension of this method is described by Rushdi.)
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Further reading

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