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Possible spell-corrected query: ESP32-sm3
A Security-Aware PQC Benchmarking Framework on Dual-Core Xtensa Silicon
Gertrude Nabasirye, Hristina Mihajloska Trpcheska, E. Fatih Yetkin
Implementation
Deploying memory-heavy post-quantum cryptography (PQC) at the smart grid edge threatens real-time substation determinism, directly conflicting with the strict $\le 3 ms$ GOOSE tripping window of the IEC 61850 standard. To resolve this architectural tension, we propose a security-aware, hardware-in-the-loop benchmarking framework on the dual-core Xtensa LX7 (ESP32-S3) SoC running FreeRTOS. To prevent inter-core resource contention, the framework employs an asymmetric task-isolation design,...
A Security-Aware PQC Benchmarking Framework on Dual-Core Xtensa Silicon
Gertrude Nabasirye, Hristina Mihajloska Trpcheska, E. Fatih Yetkin
Implementation
Deploying memory-heavy post-quantum cryptography (PQC) at the smart grid edge threatens real-time substation determinism, directly conflicting with the strict $\le 3 ms$ GOOSE tripping window of the IEC 61850 standard. To resolve this architectural tension, we propose a security-aware, hardware-in-the-loop benchmarking framework on the dual-core Xtensa LX7 (ESP32-S3) SoC running FreeRTOS. To prevent inter-core resource contention, the framework employs an asymmetric task-isolation design,...