A minimal GPU design in Verilog to learn how GPUs work from the ground up

Verilator open-source SystemVerilog simulator and lint system

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

RSD: RISC-V Out-of-Order Superscalar Processor

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

RISC-V CPU Core

RISC-V Debug Support for our PULP RISC-V Cores

4 stage, in-order, compute RISC-V core based on the CV32E40P

Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"