R port of the Scilab optimsimplex module

Complete documentation about Sandhi

Algorithm Editor and VHDL generator written with PyQt4

A simple web application for tracking employee time

GPS disciplined clock built with Arduino

GNU Radio fork v3.6

A collection of big designs to run post-synthesis simulations with yosys

Icarus Verilog GUI

A program written in Go and using plotinum that interprets raw spice files and produces pretty plots in svg, png, pdf, or jpg formats.

DXF to SVG to KICAD_PCB converter webapp that runs purely on the client side

HW: A beermat-sized PCB with FPGA, SDRAM, Hi-Speed USB & 50 FPGA I/Os

Mathematica front end to ngspice

A poor man MOSS (Measure of software similarity)

Open source IDE for embedded systems development

Netlist and Verilog Haskell Package

Algorithm to hardware compilation tools (e.g. C to VHDL).

Code to compile OpenModelica models to JavaScript

Parsing tool for OrCAD netlist files

Python bindings for ngspice simulation engine

Symbolic analysis of electronic circuits in SAGE (sagemath) starting from a SPICE (ngspice) netlist.

Eagle to KiCAD schematic conversion script.

A small set of WebApp tools for my own amusement and use in the course of EDA222 at Chalmers. Not a part of any labs, but my own created tools for the programming and verification aspects of the lab.

A very primitive but hopefully self-educational CPU in Verilog

My personal library of KiCad schematic symbols and footprints.

Fork of Andreas Unger's SPICE+ circuit simulator