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@KULeuven-MICAS MICAS (KU Leuven)

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    55 repositories

    • openising

      Public
      Roff
      •
      MIT License
      •0•1•2•0•Updated Oct 9, 2025Oct 9, 2025

    • snax_cluster

      Public
      A heterogeneous accelerator-centric compute cluster
      SystemVerilog
      •
      Apache License 2.0
      •85•30•21•8•Updated Oct 8, 2025Oct 8, 2025

    • hypercorex

      Public
      An open-source hyperdimensional computing streaming processor. It has high hardware utilization, low-cost/overhead design, and highly flexible to support various applications.
      aihdc
      SystemVerilog
      •
      Apache License 2.0
      •1•0•2•0•Updated Oct 7, 2025Oct 7, 2025

    • lagd-im

      Public
      Hardwre implementation of the ising machine chip
      Shell
      •
      Apache License 2.0
      •0•1•0•1•Updated Oct 7, 2025Oct 7, 2025

    • stream_aie

      Public
      Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
      Python
      •
      MIT License
      •30•0•0•1•Updated Oct 1, 2025Oct 1, 2025

    • mlir-aie

      Public
      An MLIR-based toolchain for AMD AI Engine-enabled devices.
      MLIR
      •
      Other
      •155•0•0•0•Updated Oct 1, 2025Oct 1, 2025

    • snax-mlir

      Public
      Driving Snax with MLIR
      Python
      •
      Other
      •4•15•2•11•Updated Oct 1, 2025Oct 1, 2025

    • HeMAiA

      Public
      The warm and cozy house for SNAX Cluster 🏠
      Tcl
      •
      Apache License 2.0
      •3•3•2•7•Updated Sep 30, 2025Sep 30, 2025

    • chisel-float

      Public
      Mixed-precision floating point units, wrapped in Chisel.
      SystemVerilog
      •
      Other
      •1•2•0•0•Updated Sep 21, 2025Sep 21, 2025

    • tech_cells_generic

      Public
      Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
      SystemVerilog
      •
      Other
      •35•0•0•0•Updated Sep 19, 2025Sep 19, 2025

    • mlir-networks

      Public
      Collection of scripts to convert neural network models into usable MLIR for use in snax-mlir
      Python
      •0•0•0•0•Updated Sep 16, 2025Sep 16, 2025

    • xdma_axi_adapter

      Public
      The AXI Adapter for the XDMA Project
      SystemVerilog
      •1•2•0•0•Updated Sep 14, 2025Sep 14, 2025

    • sunpar

      Public
      C++
      •
      MIT License
      •0•0•0•0•Updated Sep 2, 2025Sep 2, 2025

    • carbonspot

      Public
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •0•1•0•0•Updated Sep 2, 2025Sep 2, 2025

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •44•0•0•0•Updated Aug 28, 2025Aug 28, 2025

    • zigzag

      Public
      HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
      machine-learningdeep-learninghardware-accelerationmapping-algorithms
      C++
      •
      MIT License
      •50•160•14•1•Updated Aug 22, 2025Aug 22, 2025

    • .github

      Public
      README for MICAS public organization profile
      MIT License
      •0•0•0•0•Updated Aug 14, 2025Aug 14, 2025

    • zigzag-llm

      Public
      Model LLM inference on single-core dataflow accelerators
      hardware-acceleration
      Python
      •
      MIT License
      •3•14•0•0•Updated Aug 13, 2025Aug 13, 2025

    • hemaia_d2d_link

      Public
      The NoP infrastructure of future HeMAiA chips
      Other
      •0•0•0•0•Updated Aug 6, 2025Aug 6, 2025

    • accfg-artifacts

      Public
      artifact evaluation for accfg paper
      Python
      •0•0•0•0•Updated Aug 6, 2025Aug 6, 2025

    • hemaia_dimc_data

      Public
      simulation data for DIMC cluster
      C
      •0•0•0•0•Updated Jul 25, 2025Jul 25, 2025

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •180•0•0•0•Updated Jul 14, 2025Jul 14, 2025

    • gemmini-rocc-tests

      Public
      MICAS KULeuven Fork of UCB Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
      C
      •
      Other
      •48•0•0•1•Updated Jul 11, 2025Jul 11, 2025

    • stream

      Public
      Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
      Python
      •
      MIT License
      •30•59•10•2•Updated Jul 5, 2025Jul 5, 2025

    • praxis

      Public
      snax + mlir + zigzag
      Python
      •0•0•0•1•Updated Jul 3, 2025Jul 3, 2025

    • zigzag-imc

      Public
      HW accelerator mapping optimization framework for in-memory computing
      C++
      •
      BSD 3-Clause "New" or "Revised" License
      •3•25•0•0•Updated Jun 3, 2025Jun 3, 2025

    • llvm-build

      Public
      Some prebuilt compiler toolchains for the SNAX ecosystem
      Shell
      •0•0•0•0•Updated May 13, 2025May 13, 2025

    • frontend-mess

      Public
      Python
      •0•0•0•0•Updated Apr 25, 2025Apr 25, 2025

    • snax_cgra

      Public
      SystemVerilog
      •0•0•0•0•Updated Mar 20, 2025Mar 20, 2025

    • bender-feedstock

      Public
      Feedstock for bender conda package
      0•0•0•0•Updated Mar 12, 2025Mar 12, 2025