Open-source high-performance RISC-V processor

Chisel: A Modern Hardware Design Language

Rocket Chip Generator

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

Scala based HDL

RISC-V SoC designed by students in UCAS

Source files for SiFive's Freedom platforms

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

educational microarchitectures for risc-v isa

Simple RISC-V 3-stage Pipeline in Chisel

Like VexRiscv, but, Harder, Better, Faster, Stronger

OpenSoC Fabric - A Network-On-Chip Generator

CNN accelerator implemented with Spinal HDL

Labs to learn SpinalHDL

A basic SpinalHDL project

High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

SpinalHDL - Cryptography libraries

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

Chisel implementation of Neural Processing Unit for System on the Chip

A 32-bit CPU being developed in SpinalHDL