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written in VHDL
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Library of VHDL components that are useful in larger designs.
Sending UDP packets out over a Gigabit PHY with an FPGA.
Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
Collateral for an AliExpress XCKU5P dev board
Design files for an add-on board that makes a XuLA into a logic analyzer for 1.8V, 2.5V, 3.3V and 5.0V logic.