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axi

Here are 12 public repositories matching this topic...

atfox272 / DVP-RX-Controller

This repository contains the RTL code of a DVP (Digital Video Port) TX Controller with AXI4 interface in the application layer.

camera axi axi4 dvp

Updated May 5, 2025
Verilog

ZipCPU / sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface

Updated Apr 24, 2025
Verilog

atfox272 / AXI4-Interconnect

RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.

axi interconnect axi4

Updated Mar 13, 2025
Verilog

ubyhzargam / AMBA-Protocol-Family

This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm

communication-protocol verilog axi amba apb ahb amba-apb

Updated Dec 9, 2024
Verilog

kevin861222 / SOC_FIR-AXI

FIR IP with AXI-Lite & AXI_stream

soc axi digital-ic-design

Updated Aug 13, 2024
Verilog

mjh-design / AXI_DMA

一个基于AXI的DMA

ip dma axi

Updated Nov 18, 2022
Verilog

anmol109 / AMBA-AXI4-Lite

An implementation of AMBA AXI4Lite on an FPGA using verilog

fpga rtl verilog axi amba

Updated Aug 14, 2022
Verilog

lucky-wfw / ARM_AMBA_Design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

arm verilog axi amba apb ahb

Updated May 14, 2021
Verilog

mjh-design / DMA-S2MM-and-MM2S

Build an open source, extremely simple DMA.

ip dma axi

Updated Feb 17, 2019
Verilog

Wissance / QuickSPI

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Updated Nov 21, 2017
Verilog

tanerguven / StreamIF

This project is part of my master's thesis. Source code shared for the publication "StreamIF - AXI4 Memory Mapped to AXI4 Stream Interface Library"

fpga zynq axis axi

Updated May 5, 2017
Verilog

hdlguy / axi_sim

just some files that show one simple way to simulate some axi cycles.

verilog axi simulation-digital

Updated May 27, 2016
Verilog

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