RTL code for DMA controller

Knowledge hub for digital interfaces

Реализация AXI интерфейса на SystemVerilog

Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.

A presentation about Advanced Microcontroller Bus Architecture

Verilog header for easier AXI interface declaration & connection

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Synchronous and Asynchronous FIFO with AXI interface

AXI to Peripheral Interconnect

AMBA AHB 5.0 VIP in SystemVerilog based on UVM

Common SystemVerilog RTL modules for RgGen

AXI X-Bar

Xilinx AXI VIP example of use

Simple single-port AXI memory interface

Network on Chip Implementation written in SytemVerilog

AMBA AXI VIP

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication