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Send video/audio over HDMI on an FPGA
Updated
Feb 3, 2024
SystemVerilog
Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit
Updated
Oct 31, 2024
Verilog
Simplified, monocycle version of the LEGv8 processor designed by PCS Poli-USP and implemented in VHDL for Digital Systems II
Testbench for playing with the Endeavour protocol used by AMACv2.
Updated
May 12, 2018
Verilog
Module for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface
Updated
Nov 8, 2024
Verilog
HDLMake template for terasIC DE2-115
Template for use with the build tool hdlmake, specifically set up for VHDL development and simulation.
use the liteeth core on the Nexys4 board without SoC
Updated
Nov 6, 2024
SystemVerilog
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