pll
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iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter
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Nov 24, 2025 - Verilog
verilog modules
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May 4, 2020 - Verilog
This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
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Jun 2, 2022 - Verilog
A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
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May 31, 2022 - Verilog
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Apr 19, 2023 - Verilog
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