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Unicorn Engine Crash When Emulating DR7 Register Update with 0x10005
#2001
opened Sep 15, 2024 by
Z4ee
riscv: Incorrect program counter when handling exception with interrupt hook
#1990
opened Aug 28, 2024 by
apparentlymart
"System.Runtime.InteropServices.SEHException" Only in debug using Visual Studio 2022
#1982
opened Jul 29, 2024 by
gmgunderground
Instrumenting ARM code making use of hardfault handlers and especially CFSR and BFAR registers
#1971
opened Jul 8, 2024 by
r3-ck0
Execution of xgetbv instruction and setting up of the XCR register.
#1955
opened May 13, 2024 by
Nitr0-G
ARM32 Cortex A9 MRRC instruction UC_ERR_INSN_INVALID
bug
poc
#1954
opened May 6, 2024 by
TobalJackson
Ignoring a Branchs/Handling Invalid Memory Access Handling Gracefully
#1949
opened Apr 29, 2024 by
pinwhell
When running x86 simulation in unrestricted mode, there's an EFLAGS error upon exiting
#1938
opened Apr 12, 2024 by
IntThree
RISC-V64 incorrectly returns error when calling
emu_start
with count
= 1 at end of page
bug
poc
#1931
opened Mar 19, 2024 by
jxors
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