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Stars

10 stars written in Verilog
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SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,771 1,042 Updated Mar 24, 2021

alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

Verilog 2,746 791 Updated Feb 27, 2025

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,425 317 Updated Jul 16, 2025

XUANTIE-RV / wujian100_open

IC design and development should be faster，simpler and more reliable

Verilog 1,972 591 Updated Dec 31, 2021

olofk / serv

SERV - The SErial RISC-V CPU

Verilog 1,666 231 Updated Oct 17, 2025

riscv-mcu / e203_hbirdv2

The Ultra-Low Power RISC-V Core

Verilog 1,636 394 Updated Aug 6, 2025

ultraembedded / riscv

RISC-V CPU Core (RV32IM)

Verilog 1,558 270 Updated Sep 18, 2021

alexforencich / verilog-pcie

Verilog PCI express components

Verilog 1,449 372 Updated Apr 26, 2024

openpower-cores / a2o

Verilog 140 26 Updated Apr 5, 2022

JulianKemmerer / PipelineC-Graphics

Graphics demos

Verilog 112 10 Updated Mar 22, 2024